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I get an ASIC base design. The timing report as follows picture show "LOOP"
Does "LOOP" means combination loop?
How to find combination loop in Quartus tool?
I had tried Technology Map. But I failed.
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HI KFC,
What Quartus are you using? If you are using Pro, you can simply cross probe to RTL Viewer, Chip planner etc
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Hi Kfc,
May I know if there is any update?
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Hi SyafieqS_Intel
Sorry that too late to respond. I use Quartus13.1 version. I has never tried Pro.
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