How to fix "Warning (10030): Net "microcode1.data_a" at MAX10CPU.sv(10) has no driver or initial val

[BobA]

Hi,

I'm using Quartus Prime Lite 24.1 and Synplify Pro, targeting the MAX 10 10M08SCE144A7G. My SystemVerilog code is:

module MAX10CPU(
	input [15:0] address,
	output [7:0] mc,
	input noe
	);
	
	reg [7:0] microcode1 [0:65535];
	
	initial begin
		$readmemh("G:\\My Drive\\microcode1.mem", microcode1);
	end
	assign mc = (noe == 1) ? microcode1[address] : 8'bz;
endmodule

 I'm getting the warnings:

Warning (10030): Net "microcode1.data_a" at MAX10CPU.sv(9) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "microcode1.waddr_a" at MAX10CPU.sv(9) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "microcode1.we_a" at MAX10CPU.sv(9) has no driver or initial value, using a default initial value '0'

What's going on, and how can I fix it?

Thank you.

[sstrell]

EDIT: You have to use a .dat file to initialize memory in this way.

[BobA]

OK. So what's the proper way to initialize RAM from a file?

[BobA]

I figured it out ... in the IP Catalog expand On Chip Memory, select the type of memory to use, and in the wizard dialogs there's an option to initialize it to a file's contents.

[sstrell]

Yes, that's another way to do it with the memory as an IP and a .hex or .mif file.  It seemed like you wanted to do it through code inference.

[BobA]

If there's another way to do this, I love to hear about it.

I didn't really understand your previous comment about using a .dat file. The .mem file I'm using is in the format accepted by $readmemh.

[sstrell]

I've always used .dat for this.  I've never actually heard of .mem.  This article uses .txt actually: https://fpgacoding.com/test-bench-data-files-in-verilog/

[BobA]

It's just the extension. I know the file's contents are in $readmemh's format.

The bigger concern is that the 'initial' block doesn't get synthesized. But is there another way to initialize memory in the synthesized Verilog?

[sstrell · Accepted solution]

You can use synthesis attributes: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_ram_init.htm

[RichardTanSY_Altera]

Thank you sstrell for the answer.

Hi OP,

Does sstrell's suggestion helps?

Do you have further inquiry regarding this case?

Regards,

Richard Tan

[BobA]

Yes, sstrell's suggestion helped.

[RichardTanSY_Altera]

I'm pleased to know that your question has been addressed. 

Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan