How to implement a code that uses floating-point?

[Altera_Forum]

Hello, How should I do to implement in VHDL, a code that calculates the following equation: u(k) = 622,5u(k-1) + 0,6279u(k-2) + 651,2e(k) + 0,000814e(k-1) - 651,2e(k-2). I am a beginner in VHDL and do not know how to work with floating point. I think it not possible to represent the coefficients ranging from 651.2 to 0.000814 with fixed point. After implementing the code, I want to synthesize the circuit. I am using the Quartus II 64-bit Version 10.1 (Build 153 11/29/2010 ). Below, the main questions: 

 1. What libraries should I use? How do I compile the libraries? 2. How should I declare in the code variable u(k) to get a real number as a result of the equation?  Ps. I don't want to use the Nios, and the code should be synthesizable.  Thanks for the space...

[Altera_Forum]

1. You will need to use the floating point IP cores. Have a read of the user guides: http://www.altera.co.uk/literature/ug/ug_altfp_mfug.pdf 

2. It will be a std_logic_vector. THe IP cores do the work, you just wire them together.  No nios needed, a floating point calculation is perfectly usable. But expect the resource usage and latency to be quite large (probably >100 clk cycles of latency).

[Altera_Forum]

The IIR filter structure can be only implemented if the latency is smaller than the sample period. This might be a problem with float IP. 

 Generally I assume that a fixed point implementation will better serve the intended purpose.

[Altera_Forum]

Ok, thanks...I'm going to read the guide recommended.

[Altera_Forum]

--- Quote Start ---  The IIR filter structure can be only implemented if the latency is smaller than the sample period. This might be a problem with float IP.  Generally I assume that a fixed point implementation will better serve the intended purpose.  --- Quote End ---     I think it not possible to represent the coefficients ranging from 651.2 to 0.000814 with fixed point. Unless I do the staggering numbers. Am I right?? Fixed point representation uses 32 bit, right??

[Altera_Forum]

fixed point representation uses as many bits as you require. The beauty of fixed point is that it is just an integer offset by 2^n, so you can use the multipliers on the FPGA and the latency is really small (is its just integer arithmatic). 

 Also, with a massive range of co-efficients, do you really need such small ones? will they really have much of an effect on the output?

[Altera_Forum]

--- Quote Start ---  fixed point representation uses as many bits as you require. The beauty of fixed point is that it is just an integer offset by 2^n, so you can use the multipliers on the FPGA and the latency is really small (is its just integer arithmatic).  Also, with a massive range of co-efficients, do you really need such small ones? will they really have much of an effect on the output?  --- Quote End ---    I really need the small values, because they are part of an equation of the controller. Sorry, but What you mean by that "with a massive range of co-efficients" ???