VHDL 8 bits comparator using 2 * 4 bits comaparator

Altera_Forum · ‎04-14-2014

Hay everyone ,

i am trying to simulate a 8 bits comparator using 2 * 4 bits comparators here's my code .... it's compile --> no errors

but i have 3 red lignes in the wave

this is the 4bits comparator (with 3 outputs ega , inf and sup)


Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Comp_4Bits is
port(
A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
SUP : out std_logic;
iNF : out std_logic;
EGA : out std_logic);
end Comp_4Bits ;
Architecture RTL of Comp_4Bits is
begin
process(A, B )
begin
if (A> B  then Sup <='1' ; Inf <='0' ; Ega <='0' ; 
Elsif (A< Bthen Inf <='1' ; Sup <='0' ; ega <='0' ;
elsif (A= B then Ega <='1' ; sup <='0' ; inf <='0' ; 
end if ;
end process ;
end RTL;

and here is the code of 8 bits comparator


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std ;
entity compa_8bits is port(
A:in std_logic_vector(7 downto 0);
B:in std_logic_vector(7 downto 0);
ega : out std_logic ;
sup : out std_logic;
inf : out std_logic
);
end compa_8bits;
architecture RTL of compa_8bits is
signal sup1 , sup2 , inf1 , inf2 , ega1 , ega2 , sig1 , sig2:std_logic;
component Comp_4Bits is port(
A:IN std_logic_vector(3 downto 0);
B:IN std_logic_vector(3 downto 0);
ega : out std_logic;
sup : out std_logic;
inf : out std_logic);
end component ;
begin 
u1:Comp_4Bits port map
(
A =>A(7 downto 4),
B=>B(7 downto 4),
ega=>ega1 ,
sup=>sup1,
inf=>inf1
);
u2:Comp_4Bits port map
(
A=>A(3 downto 0),
B=>B(3 downto 0),
ega=>ega2,
sup=>sup2,
inf=>inf2);
inf <= inf1 or (ega1 and inf2);
sup <= sup1 or (ega1 and sup2);
ega <= ega1 and ega2;
END RTL;

and finally the test bench


        library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std ;
entity compa_8bits_tb is 
end compa_8bits_tb;
architecture BHV of compa_8bits_tb is
component compa_8bits is
port(
      A:IN std_logic_vector(7 downto 0);
      B:IN std_logic_vector(7 downto 0);
      sup : out std_logic;
      ega : out std_logic;
      inf : out std_logic  
      );
      end component;
      
      signal A, B : std_logic_vector( 7 downto 0) ;
      signal ega, inf, sup: std_logic;
begin 
Dut1:  compa_8bits port map(
   A  => A ,
   B  => B , 
   ega=>ega ,
   sup =>sup,
   inf=>inf
   );
  
   process
   begin 
   A<="11110000";
   B<="01101111";
   wait for 20 ns;
   A<="01110000";
   B<="01110000";
   wait for 30 ns;
   A<="10011111";
   B<="01101010";
   end process;
   end BHV;

thanks a lot =D

Altera_Forum · ‎04-14-2014

Once I fixed the syntax error in the first code, it worked just fine.

PS> In your testbench, do you realise the 3rd set of A and B values are not input because it loops back around to the start of the process again