Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15553 Discussions

How to improve the frequency of the running clock of FPGA?

Altera_Forum
Honored Contributor II
936 Views

Hi, 

 

After I compile my OpenCL FPGA code, I find the frequency of the running clock of the kernel is about 130MHz, how to improve it? 

 

Thanks!
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
93 Views

There is no direct control over operating frequency in OpenCL. Loop-carried dependencies and complex loop exit conditions reduce operating frequency. Also if your design is large with a high logic utilization count, that will complicate routing and reduce operating frequency.

Reply