How to instantiate a float point IP in OpenCL-HDL hybrid flow?

[Altera_Forum]

I am putting a verilog module into OpenCL, and in the verilog, a float point ip is used.  

Previously in pure HDL flow, I use .ip file with no problem. but now in OpenCL flow, seems .ip file is not supported. Then I am having problem instantiate this module.  I am using arria 10, and the ip is arria 10 naitive floating point adder with 3 stage pipeline.  What should I do? Please help.

[Altera_Forum]

I find some float point modules in hld/ip directory. These modules can be instantiated without problem. However, this didn't solve my problem, because I customized 3 stage float point adder using IP Parameter Editor. But in the hld/ip directory, there is no exact type. 

 Still expecting the answer. Can this be done by setting some parameters for twentynm_fp_mac?      --- Quote Start ---  I am putting a verilog module into OpenCL, and in the verilog, a float point ip is used.  Previously in pure HDL flow, I use .ip file with no problem. but now in OpenCL flow, seems .ip file is not supported. Then I am having problem instantiate this module.  I am using arria 10, and the ip is arria 10 naitive floating point adder with 3 stage pipeline.  What should I do? Please help.  --- Quote End ---