How to interface 1 MSPS ADC with processing module?

[Altera_Forum]

Hello everyone, 

 I have DE1-SoC board which contains 1 MSPS ADC, I am trying to take samples from ADC and process them. ADC Controller clock is 20 MHz and data is available every 16 clock cycles. The module that takes samples operates on 100 MHz clock. The problem is how can I interface these two modules?  my first thought was to use an asynchronous FIFO, but after search I figured out that it is impossible! Writing clock is much slower than reading side. I found a formula to calculate the depth of the FIFO (here (http://fullchipdesign.com/fifo_depth_formula_calculation.htm)) but it failed, giving me a negative answer! I didn't know what my "burst" is, so I assumed it to be 1 as the controller gives one sample every 16 clock cycles.  So, do you have any clue of solving this problem?  Thanks in advance.

[Altera_Forum]

Guys please! Any thought!!

[Altera_Forum]

ADC clk is 20MHz, it gives samples every 16 clks so ADC data speed is 20/16 = 1.25 Msps but you are saying it is 1Msps. 

either way you can use fifo written to at 1Msps rate and read out at same rate. then process at that rate using clk 100Mhz enabled at data rate or even you can share resource at such high clk rate available to you.  I don't think you need any rate conversion using upsamplers.

[Altera_Forum]

I'd suggest you don't need a FIFO - although a FIFO is a perfectly good way of solving it. 

 Assuming 1.25MSPS you're generating a new reading every 800ns. With a 100MHz 'processing' clock that gives you 80 clock cycles with which to process the data before the next sample arrives. That's plenty fast enough to allow you to oversample the ADC's clock domain to determine when a new sample is available. No FIFO needed.  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  ADC clk is 20MHz, it gives samples every 16 clks so ADC data speed is 20/16 = 1.25 Msps but you are saying it is 1Msps. either way you can use fifo written to at 1Msps rate and read out at same rate. then process at that rate using clk 100Mhz enabled at data rate or even you can share resource at such high clk rate available to you.  I don't think you need any rate conversion using upsamplers.  --- Quote End ---    But I think that will limit the processing speed to 20 MHz again, right? What do you mean by 'sharing resourse'?

[Altera_Forum]

--- Quote Start ---  I'd suggest you don't need a FIFO - although a FIFO is a perfectly good way of solving it.  Assuming 1.25MSPS you're generating a new reading every 800ns. With a 100MHz 'processing' clock that gives you 80 clock cycles with which to process the data before the next sample arrives. That's plenty fast enough to allow you to oversample the ADC's clock domain to determine when a new sample is available. No FIFO needed.  Cheers, Alex  --- Quote End ---    What do you mean by 'oversampling the ADC's clock domain'? Inserting zeros between samples?

[Altera_Forum]

--- Quote Start ---  But I think that will limit the processing speed to 20 MHz again, right? What do you mean by 'sharing resourse'?  --- Quote End ---    Your logic is running rocket high at 100MHz so every one clock period of 100 you get 1 sample of ADC. you got 99 left and can be used for whatever purpose.  If your 100 clk is unrelated to adc clk then you need dc fifo else you don't.