Best way is to source both clocks from the same PLL. You don't say where these clocks are coming from. Feed one into a PLL and then create two mirrored outputs.
Best way is to source both clocks from the same PLL. You don't say where these clocks are coming from. Feed one into a PLL and then create two mirrored outputs.
If they they cannot be feed into one PLL , is it possible to align two clock source with same frequency ?
I have another question, I have one pair coreclkout with 125Mhz and one input clock source with 100Mhz , how do I constrain the sdc, the latch clk 100Mhz could latch the data a few cycle later.
create_clock constraint on the 100 MHz input, created_generated_clock on the 125MHz clock. I'm not sure what you mean about latching data a few cycles later. That isn't part of defining the timing constraints for clocks.
If the clocks are sourced from the FPGA, I don't think you can use sdc constraints, you would need them to come from the same source. As mentioned in the above comment, best way is to source both clocks with a PLL.
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