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How to measure the running time in FPGA?

Altera_Forum
Honored Contributor II
‎03-25-2012 04:26 AM
1,295 Views

Hi, I am a new FPGA learner using quartus2 and stratix2 and I have a very basic question: when running circuit on the board, how can I measure the exact time needed from one state to another state, which is about 500ms? For example the time need from the condition that one register become "1" to the condition that the content of a RAM become "11001"?  

 

I am trying to use the signalTap2 logic analyzer to do it. But do not know how. Should I use this tool, or there is any other way, which is much easier? It is really appreciated if you could help me on how to measure the time! Thank you very much!!
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Altera_Forum
Honored Contributor II
‎03-25-2012 12:19 PM
565 Views

If you know your circuit, you can figure out how many clock cycles it takes. Then you just multiply it by clock period ( -- 1/frequency). 

 

You can also just simulate your circuit and measure the timings.
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Altera_Forum
Honored Contributor II
‎03-26-2012 05:12 AM
565 Views

I got the idea now... Thank you so much for your kind help! :)

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