How to purge warning message while systhesyzing dual-port rom wrote by systemverilog?

Altera_Forum · ‎05-17-2016

Hello, everyone!

I want to use a dual-port rom in my design, and initialize it with datas which depends on user specified parameter in code. So the IP core named lpm_rom couldn't be used because it could only be initialized through a .mif file generated before coding.

I copied the template code of 'True dual-port rom' from Verilog category of QuartusII's code-templates, and put them with my changing into a file named "dual_port_rom.sv" for testing, just like this:


module dual_port_rom# (parameter DATA_WIDTH = 8, ADDR_WIDTH = 8) (
    input  addr_a, addr_b
    input clk,
    output reg q_a, q_b
);
    // Declare the ROM variable
    (* romstyle = "M-RAM" *) reg rom;
    // Initialize the ROM with loop
    intial begin
        for (int i = 0; i < 2**ADDR_WIDTH; i++)
            rom = (DATA_WIDTH)'(i);
    end
    
    always @(posedge clk)
    begin
        q_a <= rom;
        q_b <= rom;
    end
endmodule

But when I synthesis it as a top module, the Quartus II reports three warning message:


Net "rom.data_a" at dual_port_rom.sv(8) has no driver or initial value, using a default initial value '0'
Net "rom.waddr_a" at dual_port_rom.sv(8) has no driver or initial value, using a default initial value '0'
Net "rom.we_a" at dual_port_rom.sv(8) has no driver or initial value, using a default initial value '0'

In the Hirachy window of Quartus II, I found that the synthesis tool had implemented this module with a core named "altsyncram".

The question is: I didn't declare any port for writing function, and even any port named with the name listed in warning message, why does the synthesis tool report those three warning? How can I purge them?

Altera_Forum · ‎03-10-2017

altsyncram has a parameter OPERATION_MODE that could be changed to "ROM". This makes those three ports not available and no warning will be reported.