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Altera_Forum
Honored Contributor I
933 Views

Type problem? Compiler doesn't help me!

Hi everyone, 

My software works for the compilation. 

But now I had a table 7seg to display my work. But it doesn't compile without error! 

I'm lost. 

My two questions are:  

questions 1):  

Why this line is not working? 

type rang0to15 is natural range (0 to 15); --With or without () have the same error message! 

--Error (10500): VHDL syntax error at LabProfBCD4Bits.vhd(25) near text "natural"; expecting "(", or "access", or "array", or "file", or "range", or "record" 

 

questions 2):  

Why this line is not working? 

Q7Seg <= Table_Nbres((0 to 15)iCntBCD); --Outgoing: 7SegLED with cast of type 

--Error (10500): VHDL syntax error at LabProfBCD4Bits.vhd(51) near text ")"; expecting "!", or "=>" 

 

Thank you in advance for your help. 

 

Part of my soft : 

--4 bits BCD counter. 

-- VHDL Language and Board: : ? (not with me right now!) 

 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

 

entity LabProfBCD4BITS is 

port( 

Clk: in std_logic; 

nReset: in std_logic; 

Q: out std_logic_vector(3 downto 0);--For testing soft in simulation. 

Q7Seg: out std_logic_vector(7 downto 0) –New version. 

); 

end entity LabProfBCD4BITS; 

 

architecture bhv of LabProfBCD4BITS is --CntBCD is 

signal iCntBCD: natural (3 downto 0);--Signal for internal computing. 

constant MaxDelay: natural :=50000-1;  

signal iCntDelay: natural range 0 to MaxDelay; 

signal CntUpBCD: std_logic;--to increment iCntBCD. 

 

--type rang0to15 is natural range (0 to 15); --With or without () have the same error message! 

--Error (10500): VHDL syntax error at LabProfBCD4Bits.vhd(25) near text "natural"; expecting "(", or "access", or "array", or "file", or "range", or "record" 

 

--type tBCD7Seg is array (rang0to15) of std_logic_vector(7 downto 0); --it doesn’t work!?! 

type tBCD7Seg is array (0 to 15) of std_logic_vector(7 downto 0); --With bit_vector, it looks also working. 

constant Table_Nbres : tBCD7Seg := ( 

-- Dpgfedcba 

"00111111", -- 0 

"00000110", -- 1 

"01011011", -- 2 

{[And so on]} 

"11111001", -- D --show "E.", means Error. 

"11111001", -- E  

"11111001" -- F 

);  

begin 

Q <= std_logic_vector(iCntBCD);--Used for simulation. Work well. 

 

Q7Seg <= Table_Nbres((0 to 15)iCntBCD); --Outgoing: 7SegLED with cast of type 

--Error (10500): VHDL syntax error at LabProfBCD4Bits.vhd(51) near text ")"; expecting "!", or "=>" 

 

--Q7Seg <= Table_Nbres(iCntBCD); --Outgoing: 7SegLED without cast of type 

--Error (10380): VHDL error at LabProfBCD4Bits.vhd(20): natural type is used but not declared as an array type  

{[The line 20 is: signal iCntBCD: natural (3 downto 0);-- 

In this case, the error is that no have a cast. Both type are different.]}
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5 Replies
Altera_Forum
Honored Contributor I
35 Views

1. This is a mix up between two things. You have a mix of subtype syntax and type syntax. A type will declare a brand new type, like an array type, or enumerated type. (0 to 15) would be used when declaring an array or an array type: 

 

eg: 

type my_array_t is array(0 to 10) of integer; 

signal sig : std_logic_vector(7 downto 0); 

 

What it look like you are trying to do, is declare a subtype, as you are limiting the range of an existing type: 

 

subtype rang0to15 is natural range 0 to 15; -- no () needed 

 

2. I dont quite know what this is - but it is not legal. And I dont know what the Table_Nbres type is. You also cannot declare a range as a type. 

Did you mean: 

 

Q7Seg <= Table_Nbres(0 to 15); 

 

This is also broken, because rang0to15 is not legal. You could write: 

type tBCD7Seg is array (rang0to15'low to rang0to15'high) of std_logic_vector(7 downto 0);, but it would be more sensible to write 

type tBCD7Seg is array (0 to 15) of std_logic_vector(7 downto 0);
Altera_Forum
Honored Contributor I
35 Views

Thank you for your answer, 

 

--- Quote Start ---  

1. This is a mix up between two things. You have a mix of subtype syntax and type syntax.  

 

subtype rang0to15 is natural range 0 to 15; -- no () needed 

--- Quote End ---  

 

 

Yes you are right. 

 

 

--- Quote Start ---  

2. And I don't know what the Table_Nbres type is. You also cannot declare a range as a type. 

 

--- Quote End ---  

 

The type of Table_Nbres is: 

type tBCD7Seg is array (0 to 15) of std_logic_vector(7 downto 0);  

 

The type of Q7Seg is : (Declared in entity) 

Q7Seg: out std_logic_vector(7 downto 0)  

 

The type of iCntBCD is: This var contains the position in the table Table_Nbres. 

signal iCntBCD: natural (3 downto 0); 

 

Now; Q7Seg <= Table_Nbres((0 to 15)iCntBCD); 

(0 to 15) is a cast for iCntBCD 

IS IT RIGHT to declar the cast like this? OR WHAT IS WRONG? 

 

Thanks for your reply.
Altera_Forum
Honored Contributor I
35 Views

signal iCntBCD: natural (3 downto 0); 

 

Is illegal. naturals and other integer types do not have accessible bits. Also, 3 downto 0 is illegal for an integer type. 

 

did you mean  

signal iCntBCD : natural range 0 to 3;  

 

 

--- Quote Start ---  

IS IT RIGHT to declar the cast like this? OR WHAT IS WRONG? 

--- Quote End ---  

 

 

You cannot do this. I still cannot quite see what you're trying to do.
Altera_Forum
Honored Contributor I
35 Views

 

--- Quote Start ---  

signal iCntBCD: natural (3 downto 0); 

 

Is illegal. naturals and other integer types do not have accessible bits. Also, 3 downto 0 is illegal for an integer type. 

 

did you mean  

signal iCntBCD : natural range 0 to 3;  

 

--- Quote End ---  

 

No, not with range. With range means, only the value 0, 1, 2 and 3 is available. AM I RIGHT? 

 

My thaught was: 

I want an unsigned integer counter with 4 bits. (And, in plus, init at 0) 

 

But if I write:  

signal iCntBCD : unsigned integer :=0;--I have a counter of 32 bits. AM I RIGHT? 

When I want to add 1 to iCntBCD, I have to write: 

iCntBCD = iCntBCD + 1 ; 

When I want to send iCntBCD to Q output, I have to cast iCntBCD, like this: 

Q <= std_logic_vector (iCntBCD);--Like I did.  

I hope it send to Q only the 4 LSB and ignorre the others bits without any error during compilation! 

 

If I want only 4 bits, I must write:  

signal iCntBCD : std_logic_vector(3 downto 0) := '0000'; -- AM I RIGHT? 

When I want to add 1 to iCntBCD, I have to write: 

iCntBCD <= (iCntBCD + '1') :--IS IT CORRECT? 

When I want to send iCntBCD to Q output, I have to do, without cast, like this: 

Q <= iCntBCD; --No cast, because both have the same type. 

 

Which methode, do you think is better? 

 

IF EVERY THING IS OK, I will modify my software and test it tomorrow, if the classroom is open. If not I will do it Monday afternoon, swiss time. 

 

I think, I'm starting to understand what's going on!  

thank you very much.  

I will send you an other message with your second answer soon.
Altera_Forum
Honored Contributor I
35 Views

 

--- Quote Start ---  

signal iCntBCD : unsigned integer :=0;--I have a counter of 32 bits. AM I RIGHT? 

--- Quote End ---  

 

 

No - there is no such thing as an unsigned integer type in VHDL. The integer type has no bits, and integer is always signed. 

 

I think you mean the unsigned type: 

 

signal iCntBCD : unsigned(3 downto 0) := to_unsigned(0, iCntBCD'length); --then add one: iCntBCD <= iCntBCD + 1;  

 

 

--- Quote Start ---  

 

When I want to send iCntBCD to Q output, I have to cast iCntBCD, like this: 

Q <= std_logic_vector (iCntBCD);--Like I did.  

 

--- Quote End ---  

 

 

Yes, you can do that - but why make Q a std_logic_vector? why not declare it unsigned and then no type conversion is needed. 

 

 

--- Quote Start ---  

 

If I want only 4 bits, I must write:  

signal iCntBCD : std_logic_vector(3 downto 0) := '0000'; -- AM I RIGHT? 

When I want to add 1 to iCntBCD, I have to write: 

iCntBCD <= (iCntBCD + '1') :--IS IT CORRECT? 

When I want to send iCntBCD to Q output, I have to do, without cast, like this: 

Q <= iCntBCD; --No cast, because both have the same type. 

 

--- Quote End ---  

 

 

You mean "0000" - ' denotes a single character, " is for strings. 

This code will only work with non-standard vhdl - it requires the std_logic_unsigned package - this is not a VHDL standard. 

 

Personally, I use the first method as that is what is required in most industry - using Standard VHDL. But I would leave the Q output as unsigned. the second method is non standard.