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Altera_Forum
Honored Contributor I
1,054 Views

VHDL 2008: Error (10500) in conditional assignment

According to my understanding VHDL-2008 should allow conditional assignment as a sequential statement, that is in clocked processes. However I get a syntax error 10500 in the below code fragment. Is that a bug in Quartus or an error on my side? In the latter case, what should the syntax be? 

 

-- altera vhdl_input_version vhdl_2008 library ieee; use ieee.std_logic_1164.all; use work.all; ... entity avs_ccm_gpio is generic( PORT_WIDTH : positive := 4; PORT_INIT : std_logic_vector ); port( areset : in std_logic; clk : in std_logic; ... GPIO_io : inout std_logic_vector(PORT_WIDTH-1 downto 0) ); end entity; architecture rtl of avs_ccm_gpio is signal CR : std_logic_vector(11 downto 0); alias CR_LAT : std_logic_vector(3 downto 0) is CR(3 downto 0); alias CR_DIR : std_logic_vector(3 downto 0) is CR(7 downto 4); alias CR_DAT : std_logic_vector(3 downto 0) is CR(11 downto 8); attribute altera_attribute : string; attribute altera_attribute of GPIO_io : signal is "-name FAST_OUTPUT_REGISTER ON; -name FAST_INPUT_REGISTER ON; -name FAST_OUTPUT_ENABLE_REGISTER ON"; begin process(areset, clk) begin if(areset) then CR <= (others=>'0'); for I in GPIO_io'range loop CR_DIR(I) <= '1' when PORT_INIT(I) /= 'Z' else '0'; -- Error (10500): VHDL syntax error near text "when"; expecting ";" CR_LAT(I) <= '1' when PORT_INIT(I) else '0'; -- Error (10500): VHDL syntax error near text "when"; expecting ";" end loop; avs_waitrequest <= '1'; elsif(rising_edge(clk)) then ... end if; end process;
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5 Replies
Altera_Forum
Honored Contributor I
49 Views

Yes this is legal VHDL 2008, but unless you're using Quartus Prime Pro 16.1, you only get limited 2008 support : 

 

http://quartushelp.altera.com/14.1/mergedprojects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm
Altera_Forum
Honored Contributor I
49 Views

Btw checking that a port is = 'Z' is not possible inside the FPGA.

Altera_Forum
Honored Contributor I
49 Views

Thanks for the reminder but my understanding was that PORT_INIT is a constant and the comparision PORT_INIT(I) = 'Z' is therefore valid. Am I mistaken?

Altera_Forum
Honored Contributor I
49 Views

I am running Quartus 16.1.1 Lite Edition.. Seems there are suble differences between Lite and Pro that I wasn't aware of (and the page you linked to does not state all that clearly - no offense intended)

Altera_Forum
Honored Contributor I
49 Views

 

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Thanks for the reminder but my understanding was that PORT_INIT is a constant and the comparision PORT_INIT(I) = 'Z' is therefore valid. Am I mistaken? 

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Didnt notice it was a constant - yes, this should work. 

 

 

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I am running Quartus 16.1.1 Lite Edition.. Seems there are suble differences between Lite and Pro that I wasn't aware of 

 

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That page I found by googling "Quartus VHDL 2008 support". Its the help from Quartus 14.1. Afaik, no extra since other than 16.1 Prime Pro has full VHDL support. The major difference between lite and Pro, other than the price, is the device support. Prime Pro has Arria/Stratix 10 support (and only these devices support 2008 I think...)