We do a lot of stuff in platform designer connecting so many complex custom ips and Altera IP's together and finally do compilation which will take over a 16 hrs - 24 hrs to generate .sof file. It's not a problem at least for the first time.
But if we make a small change in our custom RTL at least a single line of code. Again it takes 16hrs/24 hrs compilation time. we don't want this to happen again here for re-compilation in which all other IPS are not touched or not modified.
Is there a way or suggest me the technique so that it wont take huge compilation time for every run for minor modifications.
There are many techniques to save compile time. Obviously, use a "beefy" machine for compilations (multiple cores, lots of RAM) and make sure the parallel compilation feature is enabled in Quartus.
Getting to design-specific ways of reducing compile time, block-based design techniques can potentially reduce compile time:
And that includes the new fast preservation feature:
Also search for "rapid recompile".
There are training classes available for these as well:
Finally, you can use Fitter snapshots to compile up to a particular stage of the Fitter to save time (referred to as incremental optimization), but if you need to test this in hardware, that won't be as useful:
Since this thread had been answered, we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
In this pdf mentioned above. there was a link for tutorial on page no 5. which is unable to download and use. please look into that
sometimes download drops immediately and sometimes even wont starts.