How to see the content of the SDRAM in my DE1-SOC while running (JTAG Altera cable) ?

[Altera_Forum]

I have made a simple design in Quartus Prime, in verilog code, not using megawizard, but directly accessing the pins of the SDRAM. I am saving 2 x 16 bits binary numbers on 3 of the 4 banks of the SDRAM. 

 I have downloaded the design on my board DE1-SOC, and now I want to read the content of the SDRAM to see if the numbers actually passed to the SDRAM chip.  What should I do in this case?  There is a In-System memory content editor but I think it only works for on-chip RAM, or am I wrong?

[Altera_Forum]

A 'simple design'... 

 Have you implemented an SDRAM controller? Does your code issue the necessary refresh cycles etc. to keep your SDRAM happy?  Your SDRAM controller, as well as writing to memory, will have to issue the necessary command and refresh cycles to read data from it.  Does your 'simple' design do all this? Altera's own SDRAM controller IP is pretty big for a reason.  Yes, you can use the In-System memory content editor - but only if you've use the Altera SDRAM controller IP.  Cheers, Alex

[Altera_Forum]

Alex I don't meant to use the SDRAM for reading, that's why I'm looking the way to "know" the content of the SDRAM. I don't have functionally the need to use the data of the SDRAM, I just want to use it for saving data that my design is being producing cycle by cycle. 

 For practicing only , I created a simple program as follow     module sdram_try (S_DRAM_ADDR, S_DRAM_BA, DRAM_CAS_N, DRAM_CKE, DRAM_CLK, DRAM_CS_N, DRAM_DQ, DRAM_LDQM, DRAM_RAS_N, DRAM_UDQM, DRAM_WE_N, clk, rst_n, LED);   input clk; //PIN_AF14  input rst_n; // PIN_AB12    output [12:0] S_DRAM_ADDR;   output [1:0] S_DRAM_BA;  output DRAM_CAS_N;  output DRAM_CKE;  output DRAM_CLK;  output DRAM_CS_N;  output [15:0] DRAM_DQ;  output DRAM_LDQM;  output DRAM_RAS_N;  output DRAM_UDQM;  output DRAM_WE_N;    output LED;   wire [15:0] data_X1, data_X2, data_X3;   reg ref_reset, reset_source, sys_clk, enable, save_DRAM_BA, LED, save_DRAM_ADDR; reg DRAM_CAS_N, DRAM_CKE, DRAM_CLK, DRAM_CS_N, DRAM_LDQM, DRAM_RAS_N, DRAM_UDQM, DRAM_WE_N; reg [12:0] DRAM_ADDR,S_DRAM_ADDR; reg [15:0] DRAM_DQ; reg [1:0] DRAM_BA,S_DRAM_BA; reg [2:0] state, nextstate; parameter S0 = 0; parameter S1 = 1; parameter S2 = 2; parameter S3 = 3; parameter S4 = 4;     PLL_try PLL_try_inst1 ( .ref_clk_clk (clk), //  .ref_reset_reset (ref_reset), //  .reset_source_reset (reset_source), //  .sdram_clk_clk (DRAM_CLK), //  .sys_clk_clk (sys_clk)  );     RAM_IN RAM_IN_inst1 (  .data_X1 (data_X1), .data_X2 (data_X2), .data_X3 (data_X3),  .indx (S_DRAM_ADDR)  );     always @ (posedge clk or negedge rst_n) begin    if (~rst_n)   begin  enable <= 1;  state <= S0;  S_DRAM_ADDR <= 0;  S_DRAM_BA <= 0;  end  else  begin  enable <= 0;  state <= nextstate;  if (save_DRAM_ADDR)  begin  S_DRAM_ADDR <= DRAM_ADDR;  end  if (save_DRAM_BA)  begin  S_DRAM_BA <= DRAM_BA;  end    //ref_reset <= 1;  end  end           always @ (*) begin  DRAM_DQ <= 13'b0000000000000; DRAM_BA <= 2'b00;  DRAM_ADDR <= 13'b0000000000000;   DRAM_CAS_N <= 1; DRAM_RAS_N <= 1; DRAM_CS_N <= 1; DRAM_CKE <= 1; DRAM_LDQM <= 0; DRAM_UDQM <= 0; DRAM_WE_N <= 1;  save_DRAM_BA <= 0; save_DRAM_ADDR <= 0;  case (state)  S0:  begin  LED <= 0;  if (enable)  nextstate <= S1;   else   nextstate <= S0;  end   S1:   begin    LED <= 0;  DRAM_DQ <= data_X1;  DRAM_BA <= 2'b00;  DRAM_WE_N <= 0;  save_DRAM_BA <= 1;  nextstate <= S2;     end   S2:   begin  LED <= 0;  DRAM_DQ <= data_X2;  DRAM_BA <= 2'b01;  DRAM_WE_N <= 0;  save_DRAM_BA <= 1;  nextstate <= S3;   end     S3:    begin  LED <= 0;  DRAM_DQ <= data_X3;  DRAM_BA <= 2'b10;  DRAM_WE_N <= 0;  DRAM_ADDR <= S_DRAM_ADDR + 13'b0000000000001;   save_DRAM_BA <= 1;  save_DRAM_ADDR <= 1;  nextstate <= S4;   end   S4:    begin  if (S_DRAM_ADDR >= 13'b0000000000011)  begin  LED <= 1;  nextstate = S4;  end     else  begin  LED <= 0;  nextstate <= S1;  end  end   default:  begin  DRAM_WE_N <= 1;  LED <= 0;  nextstate <= S0;   end   endcase end     endmodule   I connected the pins, and I can see the LED working, but I ignore if the data is in there.  Alex, as for Altera SDRAM IP do you mean the : "SDRAM controller with UNIPHY"?.  I'm a little bit confused when generating this controller because it ask me for many signals including a group of "normal" signals and a group of "avalon" signals. The operation seems far more complex than using the RAM. That's why I was intending to use the SDRAM directly, because I think my needs of the SDRAM are quite simpler and I don't need so many control signals.

[Altera_Forum]

I'm afraid your code won't result in anything being written to the SDRAM. Your state machine doesn't do the right things to control the SDRAM. 

 Have a look, and try to understand, the sdram state diagram on this page (http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask/3). I hope it gives you an idea of the work involved.  How much data to you have to store? Could you make use of the FPGA's internal RAM?  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  I'm afraid your code won't result in anything being written to the SDRAM. Your state machine doesn't do the right things to control the SDRAM.  Have a look, and try to understand, the sdram state diagram on this page (http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask/3). I hope it gives you an idea of the work involved.  How much data to you have to store? Could you make use of the FPGA's internal RAM?  Cheers, Alex  --- Quote End ---    Alex I reduced my data and I'm using the on-chip RAM now, it compiled and loaded to the board, I'm having a unexpected issue though. Data of the third RAM is wrote with 000000000 all the way in. The first 2 RAMS are filled with the right data.  I tried this program in the modelsim first, and I'm sure the logic is correct. Do you have any ideas?  Also, I wish now to see some kind of report to know the speed of my design to complete the application.