How to setup constraint for a PWM DDR output

[Benjamin182]

Hi,

I've got a design with a master 100-MHz clock. We need a PWM with a 5-ns resolution. One solution that I've come up with is to use a DDR output block to decrease the resolution from 10 ns to 5 ns. It works well in simulation.

For example, if I want a 25 ns pulse, the input to the DDR output block will look like this

Cycle 0 : "11",

Cycle 1 : "11",
Cycle 2 : "10"

There is a delay of 10 ns between each cycles and the output will be a 25-ns pulse.

However, I'm stuck with the FPGA constraint. I don't care much about the output delay between the 100-MHz clock and the DDR output, I care mostly about the pulse width. How should I constraint my sdc?

[SyafieqS]

Hi Ben,

In Qsys, you may refer on how to constraint DDR from the example design when you use DDR IP. You can generates a design example and the design example is a fully-functional example design that can be simulated, synthesized, and used in hardware including the timing constraint if I am correct.

[SyafieqS]

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 

[Benjamin182]

Hi, I've tried your solution. Sadly the GPIO core is not available in Qsys.