How to solve Error (175001): Could not place Channel PLL when trying to use Cyclone V Native PHY IP?

[AHorn4]

Hi,

I am using Quartus II 13.0sp1 (web edition) and Modelsim-Altera 10.1d Starter Edition and am trying to integrate a Cyclone V GX multi-gigabit transceiver into one of my designs.

The Cyclone V Native PHY IP core (with reconfig and reset controllers) simulates successfully and presents no issues. However, when I combine the transceiver with a large (85% device resources) design that outputs 40-bit std_logic_vectors, Quartus II will not compile and returns the following errors:

• Error (175001): Could not place Channel PLL
•  Info (175028): The Channel PLL name: TX_NATIVE_PHY:TX_SERIALIZER|altera_xcvr_native_av:tx_native_phy_inst|av_xcvr_plls:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll
•    Error (175006): Could not find path between source fractional PLL and the Channel PLL
•       Info (175026): Source: fractional PLL pll_clk_manager:PLL_1|pll_clk_manager_0002:pll_clk_manager_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
•      Info (175021): The fractional PLL was placed in location FRACTIONALPLL_X68_Y54_N0
•       Error (175022): The Channel PLL could not be placed in any location to satisfy its connectivity requirements
•       Info (175029): 6 locations affected

         Info (175029): Channel PLL containing CHANNELPLL_X0_Y13_N9

         Info (175029): Channel PLL containing CHANNELPLL_X0_Y17_N9

         Info (175029): Channel PLL containing CHANNELPLL_X0_Y21_N9

         Info (175029): Channel PLL containing CHANNELPLL_X0_Y25_N9

         Info (175029): Channel PLL containing CHANNELPLL_X0_Y29_N9

         Info (175029): Channel PLL containing CHANNELPLL_X0_Y33_N9

• Error (11802): Can't fit design in device

To provide some context, the serialized output of the transceiver is coming out of the HSMC connector on the Cyclone V GX starter kit and I am using the Altera_PLL IP core to provide the clocks for the transceiver modules.

If anyone has encountered this problem before and knows how to solve it that would be great!

[Abe]

Well, it looks like the design cannot fit into the device. You did mention that before you integrated the IP your design had ~805 utilization. That leaves almost no space for the tool to fit the IP and also to do a Place N Route and Timing Analysis.

• Error (11802): Can't fit design in device

This error sums it all up.

You may need to

1. Re-design the rest of the code so that it takes lesser resources typically ~60% and then try integrating the IP. But this will still pose problems for Timing as the tool will not have enough resources to proceed with the timing driven place and route, etc.
2. Target another larger device in the same FPGA family, one in which your design can fit.
3. If you're using another PLL in your design, try and generate the required clock using that PLLs output.

-Abraham

[AHorn4]

Hi Abraham,

Thanks for your response. However, it turns out that the issue is related to trying to use the standard 50MHz clock signal to drive a PLL that also feeds the transceiver. It is a known problem but can be easily fixed with an intermediate clock buffer using ALTCLKCTRL IP core as described here:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd03302012_430.html

Now the design compiles and simulates with no issues.

Cheers