Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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How to solve this error while simulation?

Altera_Forum
Honored Contributor II
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Error: Can't synthesize current design -- Top partition does not contain any logic 

 

this happened when i simulated five files.....actually in have taken one top level entity file then i instantiated all four files in it...so when simulating all these I am getting error....whether this is correct way of simulating....or else is there any methods to simulate four files plz let me know....
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Error: Can't synthesize current design -- Top partition does not contain any logic 

 

this happened when i simulated five files.....actually in have taken one top level entity file then i instantiated all four files in it...so when simulating all these I am getting error....whether this is correct way of simulating....or else is there any methods to simulate four files plz let me know.... 

--- Quote End ---  

 

 

Hi, 

 

according to your error message you have a design toplevel which contains nothing. 

 

Which tool and version are you using ? Is it possible for you to post your toplevel here ? 

 

Kind regards 

 

GPK
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