Community
cancel
Showing results for 
Search instead for 
Did you mean: 
KTagh
Beginner
797 Views

How to stop Quartus Lite automatically naming new files ?

I am currently working on a simple project required for my class in where we build an Adder using Quartus Prime, but the tutorial our professor provided for us was for an older edition.

 

I have successfully made an Adder.v file that compiles with no issues. However, when I want to create a new file for the same project, the file names are automatically assigned to "Verilog1.v" or "Verilog2.v". It is important that I name this file "Adder_tb.v" because it is required for my assignment, but Quartus Prime is not letting me name the file whatever I want and it's really frustrating. What can I do here ? Thanks for the help!

0 Kudos
1 Reply
35 Views

Hi Kian,

 

Good day.

Kindly try the following steps below for creating new file for the same project.

1) File -> New -> Click 'Verilog HDL File' -> Click 'OK'

2) Click File -> Save As -> Change the File name: Adder_tb.v. 

 

I tried these steps it works for me.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Thank you. 

Reply