How to use Avalon-MM Master BFM?

[Altera_Forum]

Hello, all. 

 I want to use Avalon Verification IP Suite to check a Qsys custom componet, which have an Avalon salve interface and a Avalon conduit interface connecting a LSI.  I wrote this program to test if the custom component can give right response to the Avalon Master BFM.   //Console messaging level `define VERBOSITY VERBOSITY_INFO //BFM hierachy `define CLK_BFM top.tb.clock_source `define RST_BFM top.tb.reset_source `define MM_MASTER top.tb.avalon_mm_master `define CONDUIT_BFM top.tb.conduit_bfm module test_program(); import verbosity_pkg::*; import avalon_mm_pkg::*; event start_test; event end_test; //---------------------------------------------------------------------------------- // Set verbosity before the test starts // Qsys-generated testbench activates clock and reset BMFs //---------------------------------------------------------------------------------- initial begin set_verbosity(`VERBOSITY); // initialize BFMS `MM_MASTER.init(); end //---------------------------------------------------------------------------------- // Main test block //---------------------------------------------------------------------------------- initial begin // wait for reset inactive wait(`RST_BFM.reset == 1); -> start_test; end initial begin @ start_test; // start write access `MM_MASTER.set_command_request(REQ_WRITE); `MM_MASTER.set_command_address(16'h0); `MM_MASTER.set_command_idle(2,0); `MM_MASTER.set_command_init_latency(0); `MM_MASTER.set_command_data(32'h0,0); `MM_MASTER.push_command(); end endmodule   Although this program can be compiled by ModelSim with no error, but it seems the write access was not started.  Can you give me some hints or some examples about how to test custom components wit Avalon IP verification suite?  Regards, feng

[Altera_Forum]

Hi Joel, 

 These errors are because Altera has changed the way the SystemVerilog is compiled into libraries (the library names have changed). I was writing an Avalon-MM master/slave example last night to understand how to use the Avalon-MM burstcount interface. I'll finish that today, and then post it to this thread. I also need to update the tutorial with the latest steps for compilation.  Cheers, Dave

[Altera_Forum]

Thanks Dave!

[Altera_Forum]

Here's a quick solution to your error above: 

 Look in msim_setup.tcl and determine what library verbosity_pkg and avalon_mm_pkg are compiled into; in my case the code was compiled into both master_bfm and slave_bfm libraries (which correspond to the Qsys names I used in the example I am currently working on - your library name may be different).  Change the -L argument to vcom to match one of these libraries, and the packages will be resolved.  This is one of the "errors" in the Modelsim scripts created by Altera tools. The verification components should be compiled into a common library, eg., altera_verification_ip, not into multiple libraries that are based on the component names.  For example, if I compile using -L slave_bfm, then using the REQ_READ enumeration to the master API generates an error, since it resolves to an enumeration in the slave_bfm library ... argh! I'll edit msim_setup.tcl to create a common library and see if that helps ...  Update: I modified all the pointlessly named libraries in the msim_setup.tcl script to compile into the library "altera_verification" and then passed -L altera_verification to the compilation of the top-level testbench and to the simulation command, and now the data types in these packages resolve correctly.   I'll post code once I get my master/slave example completed.  Cheers, Dave

[Altera_Forum]

The attached file contains a Qsys system with an Avalon-MM Master BFM and an Avalon-MM Slave BFM. The testbench uses the Master BFM to issue single write/read and burst write/read transactions to the Slave BFM. 

 The readme.txt file describes how to build the system from scratch using Quartus and Qsys, and then indicates the edits that need to be made to the Modelsim simulation script (msim_setup.tcl) to simulate the top-level testbench. The readme.txt file indicates the differences between Quartus 12.1sp1 and Quartus 13.1. The Modelsim setup script is much better under Quartus 13.1 (less edits required).  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Tried the zip file and it worked for me using Quartus 13.1! The library naming was really weird from Altera. It's a big problem for someone who's trying to learn qsys and verif.  Thanks again! Extremely helpful!  r/joel

[Altera_Forum]

Hi Joel, 

  --- Quote Start ---   Thanks again! Extremely helpful!   --- Quote End ---   You're welcome.  I'm glad to hear you got it working.  Cheers, Dave

[Altera_Forum]

Hi, 

 I followed the tutorial in setting up the Avalom MM Master BFM simulation to work. I got the following error when I compile:  # ** Error: (vsim-8386) ./av_mm_master_test_program.sv(45): Illegal assignment to type 'avalon_mm_pkg.enum int ' from type 'avalon_mm_pkg@work.enum int ': An enum variable may only be assigned the same enum typed variable or one of its values.  I used the read/write tasks from the tutorial. Any ideas what may be the issue here? Thanks.    `timescale 1 ps / 1 psmodule test_program();import verbosity_pkg::*;import avalon_mm_pkg::*;//console messaging level`define VERBOSITY VERBOSITY_INFO//bfm hierachy`define CLK_BFM top.tb.pcie_de_gen1_x4_ast64_inst_clk_bfm`define RST_BFM top.tb.pcie_de_gen1_x4_ast64_inst_reset_bfm`define MM_MASTER top.tb.pcie_de_gen1_x4_ast64_inst.mm_master_bfm_0//`define av_address_w 32//`define av_data_w 32//parameter av_address_w = 32;//parameter av_data_w = 32; // ============================================================ // tasks // ============================================================ // // avalon-mm single-transaction read and write procedures. // // ------------------------------------------------------------ task avalon_write ( // ------------------------------------------------------------// input logic [av_address_w-1:0] addr,// input logic [av_data_w-1:0] data input logic [31:0] addr, input logic [31:0] data ); begin //bit [av_address_w-1:0] addr_int; //addr_int = addr; // construct the bfm request `MM_MASTER.set_command_request(REQ_WRITE); `MM_MASTER.set_command_idle(0, 0); `MM_MASTER.set_command_init_latency(0); `MM_MASTER.set_command_address(addr); `MM_MASTER.set_command_byte_enable('1,0); `MM_MASTER.set_command_data(data, 0); // queue the command `MM_MASTER.push_command(); // wait until the transaction has completed while (`MM_MASTER.get_response_queue_size() != 1) @(posedge `CLK_BFM.clk); // dequeue the response and discard `MM_MASTER.pop_response(); end endtask // ------------------------------------------------------------ task avalon_read ( // ------------------------------------------------------------// input logic [av_address_w-1:0] addr,// output logic [av_data_w-1:0] data input logic [31:0] addr, output logic [31:0] data ); begin //bit [av_address_w-1:0] addr_int; //addr_int = addr; // construct the bfm request `MM_MASTER.set_command_request(REQ_READ); `MM_MASTER.set_command_idle(0, 0); `MM_MASTER.set_command_init_latency(0); `MM_MASTER.set_command_address(addr); `MM_MASTER.set_command_byte_enable('1,0); `MM_MASTER.set_command_data(0, 0); // queue the command `MM_MASTER.push_command(); // wait until the transaction has completed while (`MM_MASTER.get_response_queue_size() != 1) @(posedge `CLK_BFM.clk); // dequeue the response and return the data `MM_MASTER.pop_response(); data = `MM_MASTER.get_response_data(0); endendtask event start_test; event end_test; //---------------------------------------------------------------------------------- // set verbosity before the test starts // qsys-generated testbench activates clock and reset bmfs //---------------------------------------------------------------------------------- initial begin set_verbosity(`VERBOSITY); // initialize bfms `MM_MASTER.init(); end //---------------------------------------------------------------------------------- // main test block //---------------------------------------------------------------------------------- initial begin // wait for reset inactive wait(`RST_BFM.reset == 1); -> start_test; end initial begin // @ start_test; // start write access/* `mm_master.set_command_request(req_write); `mm_master.set_command_address(16'h0); `mm_master.set_command_idle(2,0); `mm_master.set_command_init_latency(0); `mm_master.set_command_data(32'h0,0); `mm_master.push_command();*/ avalon_write (32'h00000000, 32'haaaabbbb ); end endmodule

[Altera_Forum]

Hi in the tutorial by David , am having problem in section 4.5.2 Avalon-MM Master BFM.  

 when i perform the following step  Compile the tutorial testbench ModelSim> vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv -L qsys_system_bfm_master  i get this error:  # Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009 # -- Compiling module qsys_system_bfm_master_tb # ** Error: c:/temp/altera_jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(48): Could not find the package (verbosity_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. # ** Error: c:/temp/altera_jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(49): Could not find the package (avalon_mm_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. # C:/altera/91/modelsim_ase/win32aloem/vlog failed. -L qsys_system_bfm_master  # invalid command name "-L"  i have tried whatever i could , but not able to proceed. Can someone help ?  Thanks in Advance!

[Altera_Forum]

This is exactly the same question as asked at the top of this forum page by Joel, to which I answered with the qsys_vip.zip a few posts above. Unfortunately Altera have changed the way they include the libraries in 13.1. 

 I recommend you unzip that file and read the instructions that it includes.  Cheers, Dave

[Altera_Forum]

Hi all, 

For my previous post, I couldn't get the solution given by david for joel working as my model sim is only 6.5 version. I'Ll download the latest and try the solution.   Thanks!

[Altera_Forum]

--- Quote Start ---   For my previous post, I couldn't get the solution given by david for joel working as my model sim is only 6.5 version. I'Ll download the latest and try the solution.    --- Quote End ---   You cannot mix-and-match. If you are using Quartus 13.1 to generate the code, then you *HAVE* to use the same version of Modelsim as shipped with that version, whether it is the Altera Starter Edition, or full Modelsim-SE edition.  I've had cases where models do not work correctly when mixing tool versions; its best to stick with the combination verified by Altera.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I am following the steps in the read me file give in the winzip folder by you , but   Quartus-generated Modelsim simulation setup script modifications   - Qsys creates the Modelsim setup script    C:\temp\qsys_vip\qwork\qsys_vip\simulation\msim_setup.tcl   I can't find this msim file in the simulation folder.  Could you tel me what might be the reason?  Thanks!

[Altera_Forum]

--- Quote Start ---    C:\temp\qsys_vip\qwork\qsys_vip\simulation\msim_setup.tcl   I can't find this msim file in the simulation folder.  Could you tel me what might be the reason?   --- Quote End ---   Which version of the tools (Quartus and Modelsim) are you using now?  Did you make sure to select the simulation option (pull-down menu) before you clicked the "generate" button in the Qsys GUI?  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Just realized that i didn't install the model sim 10.1 v, previously was running on model sim 6.5 .   Now it's there in the folder.    Thanks !

[Altera_Forum]

Hi Dave, 

 At this step:  Modelsim simulation   - Start Modelsim  - Change directory to the simulation folder    Modelsim> cd {C:\temp\qsys_vip\qwork\qsys_vip\simulation\mentor}    - Source the (edited) msim_setup.tcl script   Modelsim> source msim_setup.tcl   - Build and elaborate the design   Modelsim> ld   when i type ld i am getting the following error   ** Error: (vlog-19) Failed to access library 'altera_verification' at "altera_verification". # No such file or directory. (errno = ENOENT) # C:/altera/11.1/modelsim_ase/win32aloem/vlog failed.  Thanks!

[Altera_Forum]

As I have repeatedly stated, you *MUST* use a valid combination of tools. You have not told me what tools you are using. 

 The error message above indicates c:/altera/11.1/, i.e., version 11.1.  If you're not going to either use the version of tools clearly stated in the tutorial, or use the latest version of the tools, then its impossible to help you.  Altera changes things between versions, so its impossible to write a one-size-fits-all tutorial.  Cheers, Dave

[Altera_Forum]

Ya , sorry am using : 

 Quartus II 11.1sp1 Web Edition (32-Bit) and ModelSim-Altera 10.0c (Quartus II 11.1) Starter Edition.  Thanks!

[Altera_Forum]

--- Quote Start ---   Quartus II 11.1sp1 Web Edition (32-Bit) and ModelSim-Altera 10.0c (Quartus II 11.1) Starter Edition.   --- Quote End ---   The tutorial:  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  was written using Altera Quartus 11.1sp1 and Modelsim-ASE (Altera Starter Edition) 10.0c, so it should work just fine.  Cheers, Dave

[Altera_Forum]

Hi , 

  Am using Quartus 11.1sp1 and Modelsim-ASE (Altera Starter Edition) 10.0c.  Am following the steps given in the read me file provided in the qsys_vip.zip file in post 25 as i had the same error as posted by joel in post 21 .  But now i have tried everything , but am not able to fix the following error  # Loading ./..//submodules/bytestream_pli.dll # ** Error: (vsim-3170) Could not find 'C:\temp\qsys_vip\qwork\qsys_vip\simulation\mentor\libraries\work.qsys_vip_tb'. # Error loading design  This error arises when i try loading i.e ModelSim>ld  i checked the directory it does contain qsys_vip_tb   Can some one help me with the error , am stuck !!  Thanks!

[Altera_Forum]

--- Quote Start ---   Am following the steps given in the read me file provided in the qsys_vip.zip file in post 25 as i had the same error as posted by joel in post 21 .   --- Quote End ---    Why are you using that zip file? If you *READ* the thread, you will see    --- Quote Start ---   The readme.txt file indicates the differences between Quartus 12.1sp1 and Quartus 13.1   --- Quote End ---    You make it very difficult to help you, if you will not read, and follow instructions.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Why are you using that zip file? If you *READ* the thread, you will see    You make it very difficult to help you, if you will not read, and follow instructions.  Cheers, Dave  --- Quote End ---    Hi Dave,   Oki i'll make sure next time !    well , i tried what you mentioned in your post# 24    Look in msim_setup.tcl and determine what library verbosity_pkg and avalon_mm_pkg are compiled into; in my case the code was compiled into both master_bfm and slave_bfm libraries (which correspond to the Qsys names I used in the example I am currently working on - your library name may be different).   well i think they are in the library   ensure_lib ./libraries/qsys_system_bfm_master/  vmap qsys_system_bfm_master ./libraries/qsys_system_bfm_master/    please correct me if am wrong!   change the -L argument to vcom to match one of these libraries, and the packages will be resolved.  I changed the -L argument to vcom for the above library but still it doesn't work .   i am attaching the complete folder .can you kindly refer the msim_setup and tell me if whatever i have concluded is right?  Thanks!