I am using Quartus Prime 17.1 and I am trying to use SCLR port of the flip flop to synchronously reset the flip flop, however it synthesize a mux driven by reset input. My code is:
module ff(clk, q,a,b, reset,ce,asynch_load,data,synch_reset,synch_load); input logic clk,a,b,reset,ce,asynch_load,data,synch_reset,synch_load; logic d; output logic q; assign d = ((((q&a)|b))); always @ (negedge reset or posedge asynch_load or posedge clk) begin // The asynchronous reset signal has highest priority if (!reset) begin q <= 1'b0; end // Asynchronous load has next priority else if (asynch_load) begin q <= data; end else begin // At a clock edge, if asynchronous signals have not taken priority, // respond to the appropriate synchronous signal. // Check for synchronous reset, then synchronous load. // If none of these takes precedence, update the register output // to be the register input. if (ce) begin if (synch_reset) begin q <= 1'b0; end else if (synch_load) begin q <= data; end else begin q <= d; end end end end endmoduleAnd here is the RTL of synthesized architecture: https://alteraforum.com/forum/attachment.php?attachmentid=14868&stc=1 How could I use SCLR input to reset the flip flop value?
I don't see what the problem is... The synthesized RTL will set the output synchronously to 0 if the synch_reset output is 1, which is the definition of a synchronous reset. The registers in the FPGA don't have a dedicated synchronous reset pin if I'm not mistaken so the behaviour is created with logic around the D synchronous input.
In this old post, the code is very close to, but not exactly matching the template in Quartus that would use the synchronous reset correctly. I checked the template in the tool in 20.1 and it should be "if (!synch_reset)" instead of "if (synch_reset)" to match the active low synchronous reset of the flip-flop in the device. As such, Quartus generated extra logic to conform with this active high synchronous reset. But then the Design Recommendations user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommenda...) conflicts with that saying sclr is active high and sload is active low! So I'm not sure which combination would lead to direct connections to the flip-flop without extra logic without trying them out (and it might be different between different target devices). "1'h0" is the single bit input into sclr set to 0 to provide the active high sclr functionality specified in the code based on the synch_reset input of the design driving the select line of that mux.