I am new in VHDL and the Quartus software. I was designing a simple flip flop circuit with synchronous clear by using sequential VHDL, but in the RTL schematic, it looks like it added a multiplexer to perform the synchronous clear task and didn't use the SCLR port of the flip flop. How can I add a synchronous clear without adding extra logic, please?
here is the code of the design and the RTL schematic.
library ieee; use ieee.std_logic_1164.all; entity ff_with_sclr is port(d, clk, sclr: in std_logic; q: out std_logic); end ff_with_sclr; architecture structure of ff_with_sclr is signal qs: std_logic; begin process(clk) begin if (rising_edge(clk)) then if(sclr = '0') then qs <= '0'; else qs <= d; end if; end if; end process; q <= qs; end structure;
sclr is active high, so your if check should be if sclr = '1'. Also, there's no need for the extra qs signal. Just make the assignments to q in the process.