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14963 Discussions

How to use the SCLR port of a flip flop in VHDL?

AZahe1
Beginner
454 Views

Hi,

I am new in VHDL and the Quartus software. I was designing a simple flip flop circuit with synchronous clear by using sequential VHDL, but in the RTL schematic, it looks like it added a multiplexer to perform the synchronous clear task and didn't use the SCLR port of the flip flop. How can I add a synchronous clear without adding extra logic, please?
here is the code of the design and the RTL schematic.

library ieee;
use ieee.std_logic_1164.all;

entity ff_with_sclr is
port(d, clk, sclr: in std_logic;
	  q: out std_logic);
end ff_with_sclr;

architecture structure of ff_with_sclr is
signal qs: std_logic;
begin
process(clk)
begin
  if (rising_edge(clk)) then 
    if(sclr = '0') then 
      qs <= '0';
    else
      qs <= d;
    end if;
  end if;
end process;
q <= qs;
end structure;

quartus_UpfZc3xhao.jpg

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2 Replies
sstrell
Honored Contributor III
443 Views

sclr is active high, so your if check should be if sclr = '1'.  Also, there's no need for the extra qs signal.  Just make the assignments to q in the process.

#iwork4intel

AZahe1
Beginner
437 Views

thank you for replying.

I changed the reset to be active high, but it still uses extra logic. the only difference is that the inputs of the multiplexers have flipped.

yes right, I too think there is no need for the qs signal here.

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