How to write tcl command in sdc file for generated clock inside a component?

[Altera_Forum]

I have a system design, inside this top design, there are several components. E.g. :One of component name is "A", and its instance is "a". If there is a generated clock is clk_160ns (wire) , which is generated through a counter, the counter is drive through a 40ns clock (clk).  

 Then I try to write command in .sdc file:  create_generated_clock -name clk_160ns -source [get_ports {clk}] -divide_by 4 [get_nets a|clk_160ns]  But after I use TimeQuest, it still can not find this clock, anybody can help me to edit the tcl command?  Thanks very much.

[Altera_Forum]

You can use GUI to create the clock,then copy the command to the sdc file.

[Altera_Forum]

--- Quote Start ---  You can use GUI to create the clock,then copy the command to the sdc file.  --- Quote End ---    Yes, I try to use GUI “Insert Constraint”, but I can't find that wire I want in GUI. Any other approach?  Thanks very much.

[Altera_Forum]

Your problem is that you are trying to assign the clock to a net, and the clock is traversing through a register, which is a timing node. You cannot traverse through a timing node to do this. If you make your target of your generated clock the register bit that is driving that net, it will work as you expect. 

 create_generated_clock -name {clk_160ns} -source [get_ports {clk}] -divide_by 4 [get_registers {a[2]}]  (This assumes that bit 2 of your register "a" is what is driving the divide by 4 on the input clock).

[Altera_Forum]

--- Quote Start ---  Your problem is that you are trying to assign the clock to a net, and the clock is traversing through a register, which is a timing node. You cannot traverse through a timing node to do this. If you make your target of your generated clock the register bit that is driving that net, it will work as you expect.  create_generated_clock -name {clk_160ns} -source [get_ports {clk}] -divide_by 4 [get_registers {a[2]}]  (This assumes that bit 2 of your register "a" is what is driving the divide by 4 on the input clock).  --- Quote End ---    Thanks very much, jimbo. I think I got what you mean. If still take my design as the example, in my module instance "a", I have a 2bit counter instance "counter_a" is drived by 40 ns clock, so the the 2nd bit output of "counter_a" is the clock "clk_160ns". I should write the command as:  create_generated_clock -name {clk_160ns} -source [get_ports {clk}] -divide_by 4 [get_registers {a|counter_a[2]}]   Is that right?  Thanks.

[Altera_Forum]

Yes, that should work. I assume you already have a create_clock constraint for the input clock on port {clk}, right?

[Altera_Forum]

--- Quote Start ---  Yes, that should work. I assume you already have a create_clock constraint for the input clock on port {clk}, right?  --- Quote End ---    Yes, I do. I will try this later, if there is still problem, I will post here again. Thanks so much.