How work Quartus IP documentation generator

[JoEl]

Hi all,

I am looking for some source code documentation tool like doxygen for SystemVerilog with no luck, but I find that Quartus can generate nice HTML block design. How can I insert code in it ? I cannot find any reference about it. Is it same like description in IP library? - I don't know how to do that neither but interested in it.

If anybody can point me to some document about it I would be appreciated.

Thanks, Joe

[RichardTanSY_Intel]

Could you help to share info related to Quartus generate HTML block design? Not familiar with doxygen, but it might be similar to Intel FPGA IP library or not. You can check out the information related to Intel FPGA IP Cores, link below: https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960636914.html Hope it helps. Cheers.

[JoEl]

Hi Richard,

I had no luck with your link and got here again 😀

When you open top level project folder, with qsys in it (we have top level entity as wrapper for QSYS now) you have folder named same as your top level QSYS. See pic below and it contain information about qsys components like parameters, sw dependencies, connection, base addresses... Question is how to set those parameters cause this documentation looks usable...