I am attempting to submit a bug report for the following: Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/verilog/veriid_elab.cp...

Branden_Allen · ‎11-01-2018

Software

Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition

Suspected Manifestation of the Error

I am attempting to pass an interface to a module. This error appears when I simply pass the interface rather than a modport.

interface ifc();
   ...
  modport mp(....);
endinterface: ifc
 
module test_i(ifc a); 
    ...
endmodule: test_i
 
module test_o(ifc.mp a);
   ...
endmodule: test_o
 
module top();
   ifc A0();
   test_i T0(.a(A0));              //Crashes
   test_m T1(.a(A0.mp));    //Survives -- But Requires Many Changes
  ...
endmodule: top

Full Stack Trace

Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/verilog/veriid_elab.cpp, Line: 3543
IsFunction() || IsTask()
Stack Trace:
   0x12d17f: vrfx_altera_assert(bool, char const*, int, char const*) + 0x20 (synth_vrfx)
   0x218bfb: VeriIdDef::ElaborateSubroutine(Array*, VeriDataFlow*) + 0x75 (synth_vrfx)
   0x23ada7: VeriTaskEnable::Elaborate(VeriDataFlow*) + 0x105 (synth_vrfx)
   0x1d6bf4: VeriCaseItem::EvaluateConditions(Map&, unsigned int, unsigned int, VeriIdDef*, VeriExpression*, VeriNonConstVal*, VeriData
Flow*) + 0x430 (synth_vrfx)
   0x23f243: VeriCaseStatement::ElaborateCaseItems(Map&, unsigned int, unsigned int, VeriCaseItem**, VeriDataFlow*) + 0x209 (synth_vrfx
)
   0x240e67: VeriCaseStatement::Elaborate(VeriDataFlow*) + 0xc47 (synth_vrfx)
   0x23d255: VeriSeqBlock::Elaborate(VeriDataFlow*) + 0xbb (synth_vrfx)
   0x23ca15: VeriEventControlStatement::Elaborate(VeriDataFlow*) + 0x501 (synth_vrfx)
   0x22d4d7: VeriAlwaysConstruct::Elaborate() + 0x95 (synth_vrfx)
   0x222659: VeriModule::Elaborate() + 0x67 (synth_vrfx)
   0x222386: VeriModule::Elaborate(Library*, Map*, Array*, unsigned int, VeriScope**, unsigned int, VeriConfiguration*, BASEX_ELABORATE
_INFO*) + 0x58e (synth_vrfx)
 0x14f1a8: VRFX_VERIFIC_VERILOG_ELABORATOR::elaborate(BASEX_ELABORATE_INFO*) + 0x5f6 (synth_vrfx)
   0x145181: VRFX_ELABORATOR::elaborate(BASEX_ELABORATE_INFO*) + 0x71 (synth_vrfx)
   0x178897: SGN_FN_LIB::elaborate(BASEX_ELAB_INFO_CORE*) const + 0x157 (synth_sgn)
   0x18160e: SGN_FN_LIB::start_vrf_flow() const + 0xe (synth_sgn)
   0x181c64: SGN_FN_LIB::start(SGN_WRAPPER_INFO*) + 0x574 (synth_sgn)
   0x186530: SGN_EXTRACTOR::single_module_extraction(HDB_INSTANCE_NAME*, HDB_ENTITY*, SGN_WRAPPER_INFO*) const + 0xf0 (synth_sgn)
   0x18e318: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0x1f8 (synth_sgn)
   0x18f2d6: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist(HDB_ENTITY*, HDB_INSTANCE_NAME*, unsigned long, SGN_WRAPPER_INFO*) + 0
x546 (synth_sgn)
   0x18e3fc: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0x2dc (synth_sgn)
   0x1945e3: SGN_EXTRACTOR::extract() + 0x3a3 (synth_sgn)
   0x1a49d7: sgn_full(CMP_FACADE*) + 0xd7 (synth_sgn)
    0x1c5e6: qsyn_execute_sgn(CMP_FACADE*, std::vector<std::string, std::allocator<std::string> >&, std::string const&, THR_NAMED_PIPE*
, THR_NAMED_PIPE*) + 0x386 (quartus_map)
    0x37d61: QSYN_FRAMEWORK::execute_core(THR_NAMED_PIPE*, THR_NAMED_PIPE*) + 0x231 (quartus_map)
    0x3bcec: QSYN_FRAMEWORK::execute() + 0xc4c (quartus_map)
    0x1c75b: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x888 (comp_qexe)
    0x3025c: qsyn_main(int, char const**) + 0x13c (quartus_map)
    0x40720: msg_main_thread(void*) + 0x10 (ccl_msg)
     0x602c: thr_final_wrapper + 0xc (ccl_thr)
    0x407df: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg)
     0xa559: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (ccl_mem)
     0x8f92: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
     0x63f2: thr_thread_wrapper + 0x15 (ccl_thr)
    0x427e2: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg)
    0x20830: __libc_start_main + 0xf0 (c.so.6)
 
 
End-trace

Nooraini_Y_Intel · ‎11-22-2018

Hi,

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.

Regards,

Nooraini

MelvinSwee_T_Intel · ‎11-23-2018

hi, apologize for the delay. I will assign this thread to another engineer and will respond to you as soon as possible

KennyTan_Altera · ‎11-23-2018

Hi Branden,

Can you attached your simplified design.qar here?

Thanks

Branden_Allen · ‎11-27-2018

Apologies for my slow reply @KennyT_Intel ,

I worked around this a while ago but I will attempt to return to the revision and extract a simplified example which can be made public once I get a chance.

I am attempting to submit a bug report for the following: Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/verilog/veriid_elab.cpp, Line: 3543