I have a design that has been timing clean and stable for a while. When I make a simple change to my logic to fix an initial condition bug, suddenly my timing becomes impossible to meet. It turns out that the simple change made an array of registers (which had always been implemented as a bank of flops) look more like a RAM to Quartus II, and so it infers a RAM, but can't meet timing through it. I've tried setting the "Auto RAM Replacement = Off" assignment for the register group, but I still get the RAM.
So far, the only way I've found to get my timing back is by using a "constant read address" in some part of my logic that I don't care about so that it doesn't look like a RAM anymore.
The timing bug this has introduced, and the logic bugs I've created to try and fix it has almost caused me to miss a critical deadline. Can anyone please tell me how to get Quartus to give you what you design, instead of what it thinks would work best for you?
Thanks,
David.
