I download an example for the cyclone , when i use then example on the A10 .

[mark_lee]

I download an example for the cyclone , when i use then example on the A10 .get error like this :

Error (14566): The Fitter cannot place 6 periphery component(s) due to conflicts with existing constraints (6 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (117, 0) to (117, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): as_dclk
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)
Info (175029): AJ10
Info (175015): The I/O pad as_dclk is constrained to the location PIN_AJ10 due to: User Location Constraints (PIN_AJ10)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (117, 0) to (117, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): as_ncs
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)
Info (175029): AN10
Info (175015): The I/O pad as_ncs is constrained to the location PIN_AN10 due to: User Location Constraints (PIN_AN10)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (117, 0) to (117, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): as_data[0]
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)
Info (175029): AJ11
Info (175015): The I/O pad as_data[0] is constrained to the location PIN_AJ11 due to: User Location Constraints (PIN_AJ11)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (117, 0) to (117, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): as_data[1]
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)
Info (175029): AK12
Info (175015): The I/O pad as_data[1] is constrained to the location PIN_AK12 due to: User Location Constraints (PIN_AK12)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (117, 0) to (117, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): as_data[2]
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)
Info (175029): AK11
Info (175015): The I/O pad as_data[2] is constrained to the location PIN_AK11 due to: User Location Constraints (PIN_AK11)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (117, 0) to (117, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): as_data[3]
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)
Info (175029): AF15
Info (175015): The I/O pad as_data[3] is constrained to the location PIN_AF15 due to: User Location Constraints (PIN_AF15)
Info (14709): The constrained I/O pad is contained within this pin
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 22 errors, 2 warnings
Error: Peak virtual memory: 7055 megabytes
Error: Processing ended: Wed Nov 11 15:20:50 2020
Error: Elapsed time: 00:00:37
Error: Total CPU time (on all processors): 00:00:36
Error (293001): Quartus Prime Full Compilation was unsuccessful. 23 errors, 16 warnings

the example link:https://fpgacloud.intel.com/devstore/platform/18.1std.1/Standard/generic-serial-flash-interface-and-nios-ii-booting/

[sstrell]

Design examples are for specific development kits and devices (and Quartus versions).  If you want to adapt a design example for your own board, at least choose one that's targeted to your selected device (Arria 10).  Then there will be fewer things to adjust to match up with your own board design.

[EngWei_O_Intel]

Hi Mark

It is not recommended and not a common practice to directly port a design from Cyclone V to Arria 10. You might hit into IP incompatible, pin assignment, and configuration issues. I would suggest you to look for Arria 10 sample design or create your own design by referring to your Cyclone V sample design.

Sample design for Arria 10 (NIOS related):

https://fpgacloud.intel.com/devstore/platform/?search=NIOS&acds_version=any&family=arria-10

Thanks.

Eng Wei

[mark_lee]

The problem is solved ,thanks