Re: I have a set of output pins that needs to be constrained such that the skew between the pins is less than 2ns. How to do this ? - Intel Community

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

I have a set of output pins that needs to be constrained such that the skew between the pins is less than 2ns. How to do this ?

1,121 Views

Link Copied

1 Reply

268 Views

Hi,

You may use set_max_skew to perform maximum allowable skew analysis between sets of registers or ports.

Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_sdctmq.pdf (set_max_skew)

Thanks.

Copy link

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.