I have created pipeline multiplier and adder schematic in Quartus Prime Lite edition 16.1. During compilation it is giving error "Error (275024): Width mismatch in port "D" of instance "inst12" and type DFF -- source is ""Sum[31..16]""

[KRaut1]

Other error is: Error (275023): Width mismatch in Sum[31..16] -- source is ""Sum[31..0]" (ID Add32:inst4)"

I have named bus "Sum[31..16]" correctly coming to the input B of MUX4X. I don't know why it is giving error? Please help.

[KhaiChein_Y_Intel]

Hi,

This error indicates that the primitive for the specified instance inst12 and type DFF has a width mismatch between the source and the specified port. The number of bits of the input must be equal to that of the output. You have to check and correct the design so the input is equal to the output.

Can you try to compile in the latest version of the software, which is 19.1? If the error persists, kindly share the design QAR file for investigation. Is there any reason why you use block diagram instead of the HDL?

Thanks.

Best regards,

KhaiY

[Matin]

hi. can you help me with this error?

i will send you some screenshots.

[sstrell]

You should really start a new thread for this.  Without knowing the functionality of the block, there's no way of knowing why you are getting that error.  Post some HDL code or a lower-level schematic design so that folks here can help.

[KhaiChein_Y_Intel]

Hi,

May I know if you have any updates?

Thanks.

Best regards,

KhaiY

[KRaut1]

Sorry, I forgot to reply. The issue has been resolved. Thanks for support.