This error indicates that the primitive for the specified instance inst12 and type DFF has a width mismatch between the source and the specified port. The number of bits of the input must be equal to that of the output. You have to check and correct the design so the input is equal to the output.
Can you try to compile in the latest version of the software, which is 19.1? If the error persists, kindly share the design QAR file for investigation. Is there any reason why you use block diagram instead of the HDL?