I'm assigning a 32 bit value to a 32 bit register but getting a following warning. Warning (10230): Verilog HDL assignment warning: truncated value with size 34 to match size of target (32) Can I know what is the mistake in this.

[AM2]

The code is 

next_waddr_fifo_wdata    <= AXIMISC+32'h0088;

where both next_waddr_fifo_wdata and AXIMISC are 32 bit .

[Vicky1]

Hi,

I tried to recreate the issue you faced but I haven`t come across any warning.

Can you provide your full code?

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[Abe]

Well, this can happen depending on the value thats stored in the AXIMISC signal/register. Since you're adding two 32-bit values, there could be an overflow in the result and this is what the synthesis tool is truncating away to fit into the resultant register.

I would suggest checking the bus/bit-widths of the variables/signals in question as well as the final result of the addition to see if there is any overflow.

[CosmoKramer]

I am having similar warning. If I am confident that there is no possibility of an overflow, how can I prevent truncation?

If there was an overflow then should it not result in 33 bits instead of 34 bits?