Implementing sequential flow in AHDL

[Altera_Forum]

Does AHDL have an equivalent of the VHDL 'process' or Verilog 'always @' constructs? If not, then is there a way to model it? Thanks.

[Altera_Forum]

No and no.  

Not sure what you mean by modeling it, as process and always can do synchronous and combinatorial logic(or latches). You can do synchronous and combinatorial functions in AHDL, just not within some sort of process/always construct. It's much more structural, where you declare something to be a DFF and then directly hook to registername.clk.

[Altera_Forum]

Righto, thanks.