how to use testbench???

[Altera_Forum]

Here is my stupid question. I have a uart vhdl file. It has a testbench, also written in vhdl. How to use these testbench???

[Altera_Forum]

You need a simulation program (like Modelsim). The testbench creates an instance of your device under test (UART in your case) and at a minimum provides stimulus. It may also do some self checking. Use the testbench as your top level file in simulation. 

 Was there any documentation provided to you with the testbench?  Jake

[Altera_Forum]

I have two files. One is the uart_serial.vhd and the other one is tb_uart.vhd(testbench for my uart_serial.vhd). Set this tb_uart.vhd as top-level entity?

[Altera_Forum]

Correct - the testbench is what you select as the top level of your simulation