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Implementing sequential flow in AHDL

Altera_Forum
Honored Contributor II
‎10-01-2008 02:04 AM
1,254 Views

Does AHDL have an equivalent of the VHDL 'process' or Verilog 'always @' constructs? If not, then is there a way to model it? Thanks.

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Altera_Forum
Honored Contributor II
‎10-01-2008 04:08 AM
535 Views

No and no.  

Not sure what you mean by modeling it, as process and always can do synchronous and combinatorial logic(or latches). You can do synchronous and combinatorial functions in AHDL, just not within some sort of process/always construct. It's much more structural, where you declare something to be a DFF and then directly hook to registername.clk.
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Altera_Forum
Honored Contributor II
‎10-02-2008 02:11 AM
535 Views

Righto, thanks.

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