In VHDL, does assigning initial value for variable can be synthesized?

Altera_Forum · ‎08-17-2012

In VHDL, we can assign a value to a variable in a process like:

variable cnt : STD_LOGIC_VECTOR(3 DOWNTO 0) := -1;

Can this be synthesized or just for simulation?

Thanks very much.

Altera_Forum · ‎08-17-2012

yes, no problems with synthesis. But it will only have an effect if cnt becomes a register.

NOTE: you cannot assign -1 to a std_logic_vector. a std_logic_Vector is not a number.

Altera_Forum · ‎08-17-2012

A variable in vhdl process ends up as either register or not depending on how its value is located:

if you assign its value after it is updated then no register is synthesized.

e.g. var1 := var1+1;

data <= var1;

if you assign its value before it is updated then it implies memory.

e.g. data <= var1;

var1 := var1 + 1;

in both cases its own value is updated immediately.

Altera_Forum · ‎08-18-2012

Thanks very much, both of you.