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Incorrect FPGA speed grade in "Stratix 10 external memory interfaces" IP core (Quartus Prime Pro 17.1)

SCAND2
Novice
960 Views

Hi,

 

at the end of the synthesis of a design based on a Stratix 10 GX Development kit I get the critical warnings in the figure. The speed grade defined in the IP is the wrong one.

I'm facing the error with Quartus Prime Pro 17.1. I tried to do the same with the beta version Quartus Prime Pro 17.1ir, in this case the speed grade is correct. However, I would avoid to use the beta version. The non-beta 17.1 is the only version I can use (latest versions don't support the FPGA I'm using).

 

Thank you!

Samuele

0 Kudos
3 Replies
BoonT_Intel
Moderator
167 Views

Hi Samuele,

 

May I know what is your targeted device? I check on Quartus Pro 17.1 B240, the device with OPN-1sg280lu3f50e3vgs1 is supported.

 

I tried generate EMIF IP using this OPN in QII Pro 17.1 and perform compilation. I am still get this critical warning. From EMIF perspective both E3 and E3V speed grade is same.

Quartus give this warning because the IP still using old timing model (E3V) but latest quartus 17.1 (non Beta version) already have some timing model upgrade and it treat E3V and E3 as different model. So, it issue this false alarm.

So, I believe this critical warning can be safely ignore. I will check with development team to double confirm and get back to this thread again.

 

Last but not least, if you are generate the IP in beta version, I will suggest you to re-generate it again in non beta version.

 

Thanks

BC

BoonT_Intel
Moderator
167 Views

Yes, we confirm that this critical warning can be safely ignore.

This issue is fixed in 18.0 and above.

I tried the same step in 18.0 and this critical warning is removed.

 

*18.0 do not support device with suffix S1 (engineering sample 1), so I used S2.

SCAND2
Novice
167 Views

All right, thank you very much!

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