What's nice about the timing analyzer is that if you make a change to your .sdc without recompiling your design, you can run your timing reports as usual to see if the current post-fit (or post-synthesis) implementation from the compiler will still meet your updated timing requirements.
You do this by selecting the compilation netlist you want to use as the basis for the analysis in the analyzer. In the Lite and Standard edition, you can only choose the post-synthesis (post-map) or post-fit stages of compilation. In the Pro edition, the Fitter is broken up into different stages, so you can perform analysis at any of those stages, called snapshots, if you've enabled their generation. Turn on the "Zero IC delays" option when creating a post-fit timing netlist to see if the post-fit design will still meet timing with changed constraints.
Unfortunately, I'd say that any changes to I/O constraints would require recompilation, but you can verify that with the timing analyzer.
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