Input data pins settings for Source Synch. Interfaces

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Input data pins settings for Source Synch. Interfaces

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I have an input DDR source synchronous interface and I'm setting my PLL to source synchronous mode compensation to preserve the timing between clock and data signals at the input pins. I'm using DE2-115 dev kit, so I'm reading the Cyclone IV device handbook. There i find the following suggestion

(http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf, p. 5-23):

"Set the input pin to the register delay chain in the I/O element to zero in the

Quartus II software for all data pins clocked by a source-synchronous mode PLL.

Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II

software."

Does anyone know how can I accomplish these settings?

Thank you in advance for any help you can give me.

Regards,

Lorenzo

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