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Hi,
I am trying to compile& simulate VHDL code for a multibit adder along with its testbench. The code is tested in Questasim and it works fine however Questasim is giving errors which I can't quite figure out how to fix them.
If anyone knows how to fix these, that would really help.
My code and screenshots of the error is attached in this question.
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Those aren't errors, only warnings, so they should not prevent compilation in Quartus.
Your design is purely combinatorial, so that's why there's a warning about no clocks.
I don't know how you have your Quartus hierarchy set up, but you do not compile a testbench in Quartus. That's only for simulation, so don't include the tb file in your Quartus project.
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so what about if you wanted to simulate you code first using Questasim? Intel Quartus does the option for running a rtl simulation, correct?
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Quartus can generate script files so you can simulate in Questasim. It doesn't do a simulation compilation.
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May I know any update?
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Hi,
Glad to hear that your issue has been resolved.
I'll now transition this thread to community support.
If you have a new question, feel free to open a new thread to get the support from Intel experts.
Thank you.
Best regards,
Sheng

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