I am trying to compile& simulate VHDL code for a multibit adder along with its testbench. The code is tested in Questasim and it works fine however Questasim is giving errors which I can't quite figure out how to fix them.
If anyone knows how to fix these, that would really help.
My code and screenshots of the error is attached in this question.
Those aren't errors, only warnings, so they should not prevent compilation in Quartus.
Your design is purely combinatorial, so that's why there's a warning about no clocks.
I don't know how you have your Quartus hierarchy set up, but you do not compile a testbench in Quartus. That's only for simulation, so don't include the tb file in your Quartus project.