Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Inter-Path Competition (Beginner Question)

Altera_Forum
Honored Contributor II
2,486 Views

Hello all, 

 

I've recently started using Quartus II 15.0 Web Edition for a class I'm taking, and I've run into a recommendation I can't figure out how to address. I'm trying to extract timing information from my circuit, but I keep getting a warning that says the timing requirements aren't met, and it tells me to run "Report Timing Closure Recommendations" for details. When I do, I get the following message: 

 

"Duplicate the nodes specified in the details for the path from wrapper_norm_corr..._reg_3|dout_1[5] to wrapper_norm_corr...3|lrexrre_reg[0]" 

 

So, my super basic question is this: how do I duplicate nodes? Any help would be greatly appreciated.
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Altera_Forum
Honored Contributor II
1,040 Views

i was also searching answers for this duplication thing in quartus prime 15.1 .........and by looking at your post i think ergowar you are still waiting for the same answer ......

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Altera_Forum
Honored Contributor II
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First I believe you have to explicitly code the duplicate registers. This means that if you have a register called test_reg that fans out to 20 destinations you would create extra copies that are logically identical but are wired up to different destinations (test_reg_a, test_reg_b, etc). You have to code the fanouts yourself. 

 

Then go into Assignments -> Settings -> Compiler Settings -> Advanced Settings (Synthesis). There's a setting in there called "Remove Duplicate Registers" that is enabled by default. You need to disable that so that your duplicate registers don't get optimized away. 

 

I believe this is the best way to handle this. If not then hopefully someone else will chime in. 

 

Bob
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