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euem789
Novice
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Is there a Synthesizable syntax with writing file in verilog??

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Hi guys,

 

Now I'm Using

--------------------------

Software : Quartus 18.1

Board : DE1 - Soc

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I'm facing problem with FILE IO in verilog . (

what I want to do is making an output file with synthesizable syntax (targeting the implementation of FPGA board Not for simulation)

here's the code I wrote.

 

module readmem(clk);
	input clk;
	
	reg [7:0] rmem [0:2];
	reg [7:0] wmem [0:2];
	
	initial begin
		$readmemb("C:\\test_num.bin",mem);
		$writememb("C:\\test_num_reslut.bin",wmem);
		
		wmem[0]=(rmem[0]<<1);
		wmem[1]=(rmem[1]<<1);
		wmem[2]=(rmem[2]<<1);			
	end
endmodule

 

After compile what I expected  was generated  output file 'test_num_result.bin'  but nothing happend.

 

I heard that $readmem syntax is able to synthesize( also used for memory initialization),  and there was no problem with compilation.

and no error with $writemem syntax too.

 

Could someone tell me am I doing right??

I'll be really appreciated if someone tell me what's wrong....

 

and furthermore,

- Is it possible to perform only with verilog in quartus??

  or do I have to use a soft processor (NIOS) ??

( What I'm trying to do for my project is reading a image file with applying sobel-mask and then, making an output file through my FPGA board)

 

thanks for reading

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Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY