Now I'm Using
Software : Quartus 18.1
Board : DE1 - Soc
I'm facing problem with FILE IO in verilog . (
what I want to do is making an output file with synthesizable syntax (targeting the implementation of FPGA board Not for simulation)
here's the code I wrote.
module readmem(clk); input clk; reg [7:0] rmem [0:2]; reg [7:0] wmem [0:2]; initial begin $readmemb("C:\\test_num.bin",mem); $writememb("C:\\test_num_reslut.bin",wmem); wmem=(rmem<<1); wmem=(rmem<<1); wmem=(rmem<<1); end endmodule
After compile what I expected was generated output file 'test_num_result.bin' but nothing happend.
I heard that $readmem syntax is able to synthesize( also used for memory initialization), and there was no problem with compilation.
and no error with $writemem syntax too.
Could someone tell me am I doing right??
I'll be really appreciated if someone tell me what's wrong....
- Is it possible to perform only with verilog in quartus??
or do I have to use a soft processor (NIOS) ??
( What I'm trying to do for my project is reading a image file with applying sobel-mask and then, making an output file through my FPGA board)
thanks for reading
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