For an FGPA fabric AvalonMM master, it is very important that the base addresses be correctly defined in a HDL source file so it can make use of them. The base addresses can change easily as we make some modifications in the Qsys system.
The base addresses are stored in the .sopcinfo file which is basically a XML file by the look of it. Although I can come up with my own tcl or python based solution to extract the base addresses from this sopcinfo file, is there a standard way to extract the base addresses into a VHDL/Verilog/SystemVerilog file e.g an already existing tcl, perl or python script that can be executed as soon as the user presses the compile button and update the HDL file from the sopcinfo file?
Updating the base addresses manually by reading them from Qsys and writing them into a HDL file is prone to errors and is not reliable.
When you generate a system in Platform Designer, the main output is the HDL files that define the interconnect and the components that connect to it. It's in the folder named after the system. This HDL should already include the addressing in it and includes a top-level file for instantiating the system into a higher-level design. What do you need the separate HDL you mention for?
The VHDL written FPGA fabric master has multiple AvalonMM master ports that are connected to multiple peripherals which are shared with a Nios that also connects to them. When the FPGA fabric master wants to perform a read/write it shall take the base address of the desired peripheral and add the offset for the register to be accessed. This information is available to the Nios from System.h file. How does a fabric based master get it? The base addresses should exist in a VHDL package version of the System.h which can be included into the VHDL of the custom fabric master. I hope it is more clear why I need this.
In Qsys we have a tab for "address map". I just need this information to be put into a VHDL package automatically when compilation starts!
In plarform designer, once you assign base address, interconnect, etc, the HDL generated (verilog or VHDL) which is the output, there would be address, interconnect component, top level in it. If there is changes in base address in sopinfo, reassign the address and generate the HDL again.
I have design a custom fabric master that needs to know the base address of each peripheral before it can access them. The base addresses would come from a package. This custom fabric master is written in VHDL and will have multiple Avalon master ports connected to different peripherals.
Which Qsys automatically generated VHDL file stores the base address for each peripheral connected to each AvalonMM master port of the RTL based FPGA fabric master? I have not found it yet.