The Quartus FMAX only shows frequencies of clocks the compiled design can run up to but does not show what the clock frequencies are constrained in the .sdc file or derived from PLL. While such info can be dug out by going .sdc files and each of the PLL IP generation page it is inconvenient and prone to mistake. Is there any way for the Quartus to show the constrained/derived frequencies? The best is to have such info in a column in parallel to the FMAX, and if not, any other way? Thanks.
In the timing analyzer, generate a clock report (report_clocks). That shows a summary of all the clocks in your design.
In case you're not familiar with the tool, check out these trainings:
Thanks for the great help. The report_clocks provides great amount of detail. For example, when Fmax lists only 22 clocks, report_clocks lists all the 248 clocks. Suggest Intel to add Ftarget (from .sdc file and its derived, for the same clocks that Fmax lists, for example, 22 clocks) and Fdelta columns in the Fmax panel next to the Restricated Fmax column and when a Ftarget is not met the Fdelta is shown negative number in red color.
Another suggestion is for Intel to allow user to add buttons to its GUI to link to any tcl scripts, for example, adding a Report Clocks button that when clicked executes the report_clock … tcl command. Both WIndows and Linux should have already made it easy for application to add such capability.
If any path in a clock domain is failing timing based on the design and your .sdc, the clock will show up as red when you run a summary report.
You can run Report Clocks directly from the Tasks window; no need for any extra buttons.