Re: Issue when converting between multiple data types - Page 2

Altera_Forum · ‎11-28-2012

Hello everybody I have an issue with this one line of code here:


output(to_integer(unsigned(msbd) + unsigned(lsb)) downto 0) <= bit_field(to_integer(unsigned(msbd) + unsigned(lsb)) downto to_integer(lsb));

bit_field and output are 32 bit std_logic_vector

msbd and lsb are 5 bit std_logic_vectors

Issue is when I convert the VHDL file to a symbol file I get this:


Error (10405): VHDL error at aluvhdl_entities.vhd(896): can't determine type of object at or near identifier "to_integer" -- found 0 possible types

Can some one tell me what the issue is?

Altera_Forum · ‎12-04-2012

what this code tells me is that you are making things far more complicated than they need to be regarding type conversions.

How about using the appropriate types in the first place rather than std_logic_vector? Your code just looks a mess.

Altera_Forum · ‎12-04-2012

You can also use a loop, and decide where the bits are coming from with an if -elsif - else statement inside that loop.

The code now gets bigger, using 740 LCs.

I feel that a solution using barrelshifters and simple logic operators will be a lot smaller, and probably also faster (using less levels of logic)

Altera_Forum · ‎12-04-2012

I agree with Tricky std_logic vectors should only be used when you indeed have a vector signal that represents something else than a number, or for interfacing with other components that require everything to be std_logic/std_logic_vectors. For the rest, use ranged integers for signal that never need to be converted to std_logic_vectors, and the signed/unsigned types for those that need to.

Altera_Forum · ‎12-04-2012

To Tricky and Daixiwen: criticising Alegomaster's coding style doesn't help him.

Yes he is making it difficult by using intermediate 'integer' objects. But he'll learn - like we all did and (hopefully) still do.

In his case std_logic_vectors are the most appropriate representation to use: he actually wants to insert a part of a 32-bit vector into another 32-bit vector at a certain place . You would have noticed if you actually tried to understand the given code.

Altera_Forum · ‎12-05-2012

The issue I have is I am wondering if there is anyway to do this other then some for while loop.

EDIT: I am trying to do it now but I am having issues figuring out how to do the insert_value value. I am probably making it a std_logic_vector so that I can easily concatenate it however I don't know how to do it so that std_logic_vector can have a dynamic size. I guess I will have to do a more complicated concatenation operation to make it work. On the other hand a massive for loop may work...

EDIT 2 : I got it to compile! Here is the code I did:


for i in 31 to 0 loop
if i >= msbd + 1 OR i <= lsb - 1 then
output(i) <= destination_register(i); 
else
output(i) <= destination_register(i + to_integer(lsb));
end if;
end loop;

EDIT 3: RTL viewer seems to improperly display the circuit. I am sure it is different then this...

https://www.alteraforum.com/forum/attachment.php?attachmentid=6543

I am connecting the circuit externally so I am wondering what is wrong... I know one issue that may be causing it

EDIT 4: Nope its not that issue... I am confused...

Altera_Forum · ‎12-05-2012

To joysb: it was constructive criticism, and I think it does help. Making lsb, msb and destination_register unsigned instead of std_logic already removes a lot of conversions in the code, and makes it easier to read and debug.

To alegomaster: you are on the right track, using a loop is the best (only?) way to do concatenation of vectors with dynamic size. You just overlooked something:31 to 0this range is empty. It should either be 0 to 31 or 31 downto 0. Don't worry, we all make this mistake at least once ;) Quartus has probably put a warning about this, but it writes so many warnings it is easy to miss it. But hopefully it should synthesize correctly after this modification.

Altera_Forum · ‎12-05-2012

Edit1: In VHDL no object can have a dynamic size.

Edit2 and 3: This is what I tried yesterday before giving you the hint. It looks a bit like your code, and generates a big RTL diagram and use quite some LCs

process( source , destination , msbd , lsb )
            variable si : natural ;
        begin
            output <= (others => '0') ;
            si := 0 ;
            for i in 0 to 31 loop 
            
                if ( i < to_integer( unsigned( lsb )) ) then
                    output(i) <= destination(i) ;
                elsif( i < (31 - to_integer( unsigned( msbd ))) ) then
                    output(i) <= source(si) ;
                    si := si + 1 ;
                else
                    output(i) <= destination(i) ;
                end if ;
                
            end loop;
        end process ;

I didn't restrict si's range, but that doesn'y change anything, neither in the RTL-diagram, nor in the amount of LCs (edit)

I didn't spot the '31 to 0' error, as Daixiwen did.

Another way to do the same:

It assumes you have a barrelshift component (look in Pedroni's Circuit Design with VHDL' page 187 ff.). The other operators are standard. Except the reverse function, which is is easy to write with a loop. The RTL diagram will be small and understandable, and it will use a lot less LCs.

Altera_Forum · ‎12-05-2012

calling somebody else's code a mess was what I meant by not being too helpful.

I'm a bit of a purist and using an unsigned type just to avoid typing is not a good reason (to me). But using an unsigned for the lsb an msbd makes sense, then again the source and destination are perfectly represented by a std_logic_vector. Now alegomaster is developing an Alu (I believe) so the lsb and msb are probably slices of an std_logic_vector, so it comes down to deciding where to put the conversion function, at the 'slicing them' of at 'using them'.