Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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JIC files and memory maps

Altera_Forum
Honored Contributor II
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I have a board with an EP3C16 that is hosting an 8-bit micro-controller core. I have allocated 32kB of the internal BRAM for code, and another 4K for data, though I may reduce the size of the data portion. The BRAM is fairly well spoken for by peripherals, so at this point, I am looking at paging in code as needed. 

 

I would like to store additional pages of code in the attached M25P16 flash memory, which I specifically oversized for this purpose. The problem is, I can attach additional HEX files to the JIC file, but I don't know how the internal memory is organized, and I do still need to boot the FPGA. 

 

I would like to set it up so that code pages are organized on page boundaries in the flash, so as to simplify access, but I'm not sure how to set the tool up to do that. Is there an application note that describes how the flash memory is organized in this case?  

 

Thanks!
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