Large clock skew

[Altera_Forum]

Hi, I have a serial signal entering my FPGA. It's generated by a 60MHz clock on another, off-board component. 

It's latched in by a 240MHz clock in my FPGA, generated by a PLL. However, in Timequest it is reporting a -4.514 clock skew on this 240MHz clock to the latching register! I have Auto-global turned on in settings. I'm not sure what could be causing this amount of skew, and I'm not sure how to resolve it. Any help would be appreciated.  Thanks!

[Altera_Forum]

Hi, 

 did you constrain the input delay in TimeQuest? If so, how? Did TimeQuest throw any warnings? I would generally not trust the TimeQuest report if there are any warnings about ignored (i.e. erroneous) constraints.   Best regards, GooGooCluster

[Altera_Forum]

IO ports generally have clock skew. The clock delay inside the FPGA to the latch register is some real delay(input buffer -> clock tree, etc.) and probably 4.514ns. The external register that launches the data has a 0ns clock delay. So all clock delay inside the FPGA shows up as skew(unlike internal paths, that have clock delay to both launch and latch registers which generally cancels out). So this pretty normal. If it's failing timing because of this clock skew, add a PLL if there isn't one, phase-shift the PLL back(or do a positive phase-shift and multicycle of 2, which is the same thing) or take it off a global. 

(And note that it's not like the external device doesn't have clock skew. It's just more common it's hidden. For example, the external device might have a Tco max of 6ns, which under the hood might be a clock skew of 3.5ns and register to output of 2.5ns, but the whole thing is just listed as 6ns and put into the set_input_delay -max value.)

[Altera_Forum]

Thanks Rysc. I'm going to add a PLL to the 240MHz and phase shift it back to see if that allows me to resolve my timing issue.