HalloI am using MATLAB and Simulink to create my model and the using the HDL coder to generate HDL code for Altera FPGA. We have a custom hardware made from ep4ce22f17c6n with I2S interface and other necessary stuffs. We need to implement a FIR filter with around 8192 coefficients for one of our filtering requirements. But as i mentioned i am currently using MATLAB and Simulink, Simulink does not support generation of filters with more than 1024 coefficients. I also tried a way to make the filter in MATLAB in different approaches but ends up using too much resources. I found out about the ALTERA FIR compiler, and it can make FIR filters up-to 2046 coefficients. Would it be possible to cascade several (7-8) filters of 1024 coefficients. The final question is it actually possible to build a such a long FIR Filter in FPGA, we dont need much of the other resources from the FPGA, filtering would be the biggest task in this project. If i am in the wrong thread, please suggest me the correct thread to post this question. Thanks in advance
Pretty drastic filter. It will require large ram (e.g. 8192 *16bits). And no way to get 8192 mults in any basic fpgaIf you can clock fast you can use MAC approach. cascading of a filter is possible but requires Z domain factorisation. You ay also be helped by the principle that h = conv( h1,h2) i.e. a cascade of h1,h2 is equivalent to h
Hithanks for the reply. Yes i know that no FPGA has 8192 multipliers. Can you please give me an idea what you mean by the MAC approach. I tried the attached code, the idea was to break the 8192 taps filter into small filters with 1024 taps. I am using a circular buffer data input and the pass the data through the cascade. But it does not generate code in the HDL coder. I tried loop unrolling and sharing optimizations but no success. If possible please have a look at the attached file.
--- Quote Start --- You didn't mention the sampling frequency. The long filter can be implemented with moderate resource requirements for lower speeds. --- Quote End --- Hi the Fs would be 44.1 kHz for now. if possible we would like to go upto 96 kHz but then the filter coefficients are also getting double almost
--- Quote Start --- Hi the Fs would be 44.1 kHz for now. if possible we would like to go upto 96 kHz but then the filter coefficients are also getting double almost --- Quote End --- if you run a clock @ 100MHz then you have a ratio of 100MHz/44.1KHz ~= 2000 and you can then use MAC i.e. multiply accumulate sharing same mult for 2000 computations. so you will need 5 mults or so