Making Nodes visible to SignalTap

[SparkyNZ]

When I want to view nodes in SignalTap, I sometimes have to comment out my nodes and put them into module outputs and then into top level outputs in order to see them.

Isn't there an easier way of decorating a node so that it can be forcibly available to SignalTap?

e.g.

/* Moving to module outputs so I can see on SignalTap..
bit [9:0] screen_last_active_hpixel;
bit [9:0] last_active_hpixel;
bit [9:0] screen_hstart_pixels;
bit [9:0] last_screen_hpixel;
bit [9:0] horiz_border_pixels;
*/

module VgaDisplay(
input logic notReset, // K4 switch on PS-06 board
input logic clk25,
output logic red,
output logic green,
output logic blue,
output logic oVSync,
output logic oHSync,

output bit [9:0] vic_screen_last_active_hpixel, // TEMP - so I can see in SignalTap
output bit [9:0] vic_last_active_hpixel, // TEMP - so I can see in SignalTap
output bit [9:0] vic_screen_hstart_pixels, // TEMP - so I can see in SignalTap
output bit [9:0] vic_last_screen_hpixel, // TEMP - so I can see in SignalTap
output bit [9:0] vic_horiz_border_pixels // TEMP - so I can see in SignalTap

[FvM]

Hi,
registers that are only used for Signaltap can be prevented from being discarded during synthesis by noprune synthesis attributes, detail description in Quartus handbook, chapter Quartus Integrated Synthesis.

Verilog-2001 and SystemVerilog:
(* noprune *) reg my_reg;

[SparkyNZ]

Unfortunately that doesn't seem to work:

(* noprune *) bit [9:0] vic_screen_last_active_hpixel;
(* noprune *) bit [9:0] vic_last_active_hpixel;
(* noprune *) bit [9:0] vic_screen_hstart_pixels;
(* noprune *) bit [9:0] vic_last_screen_hpixel;
(* noprune *) bit [9:0] vic_horiz_border_pixels;

As you can see, the existing nodes in SignalTap turned red and I cannot locate the new ones marked with (* noprune *) :

I tried /* synthesis keep */ and /* synthesis preserve */ from the notes I'd made some time ago - but in my notes I stated that I had problems trying to get nodes to appear  and the only way I could get it to work was to make output signals in the module header instead.

Does it only work with the reg keyword perhaps?

[sstrell]

If you're using the pre-synthesis Signal Tap filter, make sure you've run at least Analysis & Elaboration again after making any code changes.

Also, with this filter, you shouldn't have to worry about nodes getting optimized away.  That's usually only an issue if you are trying to tap post-fit nodes because you want them to be preserved through the compilation process.

Also, it's strange that you say you can tap top-level outputs because normally you specifically can't do that because there's no path back into the device from an I/O element.  You would want to tap the register that was feeding the output instead of the output itself.

Another thing to try is to use virtual pin assignments in the Assignment Editor.  That connects a signal node to stub logic to avoid getting optimized away during compilation even if the signal is not meant to ever connect to a top-level I/O.

[SparkyNZ]

Yes I normally just do the "Start Analysis and Elaboration" when adding new nodes, to get SignalTap to have visibility of them. Right now I'm compiling the whole thing, shutting down SignalTap and restarting SignalTap but it still won't show those nodes with the Pre-Synthesis filter.

I think the Virtual pin assignment would take longer to do as well - these days I edit my Verilog with Notepad++ so I have access to keyboard macros and the likes to speed up editing.

[sstrell]

What logic are those nodes connected to?  There must be a reason why they are not showing up in the Node Finder.

Also, what does editing your design in Notepad have to do with creating assignments for your Quartus project in the Assignment Editor?

[SparkyNZ]

The only reason I mentioned Notepad is that I find editing text faster than going into the Quartus UI screens. Just saying that if I can "decorate" registers/nodes withing the Verilog text, that's easier than fiddling with the Assignment Editor.. However.. I do seem to have hit the pin limit where I may need to do what you suggested anyway:

What is my logic connected to? Well.. I had hardcoded a load of constants that need to become variable. Once I did that, the logic didn't seem to work the way I expected it to so I thought I would "promote" the nodes to outputs so I can see what values they are taking on in SignalTap..

Maybe I have far too many interdependencies here and perhaps I need to take a step back and simplify what I have.

The last 5 signals I refer to in my VGAController module - it decides where to paint a border or a screen background.. as the old Commodore Vic 20 used to.

I know what I am doing it bad because I am including so much arithmetic now. It wouldn't have mattered with the constants.. but pretty bad to implement that complicated mess in logic.

[sstrell]

Editing your design code has nothing to do with project assignments.  You have to either use the Assignment Editor or edit the .qsf file directly.  Is that what you mean?

Anyway, looking at that code, you should really try registering those signals.  That will certainly guarantee that they will be tappable in Signal Tap.  It looks like you're just doing a bunch of math and not generating any logic.

[SparkyNZ]

When you say "registering those signals", what do you actually mean, sorry?

Here's another case for example:

bit [7:0] vic_screen_lines;
assign vic_screen_lines = vicScreenCharHeight << 3; 

I have other assign statements that use vic_screen_lines but I cannot view them in SignalTap.

I tried this too but it made no difference:

(* noprune *) reg [7:0] vic_screen_lines;

[sstrell]

I mean supply a clock and create registers to store the values. Basic RTL design practice.

[SparkyNZ]

Oh, so if the registers aren't modified on a clock cycle (ie. within an always block or state machine), then maybe registers are not inferred? Is it possibly because I have "continuous" logic here rather than clocked (flip-flop) logic?

Please excuse my limited experience - I'm still a beginner/dabbler. Maybe it would be good for me to scale down a smaller project and see what is actually produced in the RTL Viewer.

[ShengN_Intel]

Hi,

May I know does the problem resolved after registering those signals?

Thanks,

Regards,

Sheng

[SparkyNZ]

No, the issue with SignalTap not showing the values is not resolved. I am busy trying to fix my logic overall - I can still only track outputs from my modules. I cannot track other nodes such as the ones mentioned earlier.

[FvM]

Hi,
the only explanation why noprune doesn't work for these nodes is that they are not registers or not reside in the respective module.

E.g. assign vic_screen_lines = vicScreenCharHeight << 3; surely doesn't infer registers or combinational logic cells, just alias bits for vicScreenCharHeight, whatever it is. If it's a constant, it won't be accessible by Signaltap.

As stated by sstrell, storing it in a register with noprune attribute will surely make it visible, except for the lower bits which are constantly zero and thus discarded.

Regarding pin limit for port signal, you might declare the respective ports as virtual pins in assignment editor, doesn't consume pins but keeps the port.

Regards

Frank

[ShengN_Intel]

Hi,

I try with either reg/logic without clocking like below, but still can find the node in STP.

reg/logic [3:0] intermediate;

assign intermediate = a & b;

assign y = intermediate ^ a;

Have you try preserve for debug check this link https://www.intel.com/content/www/us/en/docs/programmable/683236/21-3/preserving-signals-for-monitoring-and.html?

In STP, may be can use the filter Design Filter (all names).

Have you check the optimization result report, does the nodes being optimized away?

[SparkyNZ · Accepted solution]

I tried (* preserve_for_debug *) in VgaDisplay.sv but that still won't show vic_screen_lines in STP. I tried "Design Filter (all names)" as well - it still doesn't appear when I click List.

It is not listed in the 2 optimization result reports for removal, I can't find it in the compilation output, and I certainly can't see it in the RTL Viewer so it must have been removed somehow.

BUT.. I have just this minute tried searching for *vic_screen_lines* - and it appears! So I will have to remind myself to always use the asterisks either side of the node. I feel so stupid now - thank you for joining on me on this journey.

Always surround with asterisks, Sparky! Always!