Master Addressing Issues

[Altera_Forum]

Hey everybody, 

I have a question concernig the Avalon-MM Master Interface in Qsys. My Datawidth is 32 Bit and so I have a 4 Bit Byteenable Signal. My Adresswidth is 32 Bit, too.  If I understood the Avalon Bus correctly, my Master should only do aligned addressing (0x00, 0x04, 0x08,...).  Here is my question now: Does this aligned adressing concern to Byte adresses oder (for my 32 Bit Master) double word adresses? Is it wrong if I send the DoubleWord Address 0x01 (meaning 0x04,0x05,0x06,0x07 in Byte Adressing) instead of sending the Byte Adress 0x04?  I hope you can understand what I mean.. Thanks so far. Michl

[Altera_Forum]

Avalon bus always use byte addressing. 

Then for doubleword (32bit) accesses you will only use multiple-of-4 addresses: 0, 4 , 8, ... Similarly, for word (16bit) accesses you only use multiple-of-2 addresses: 0, 2, 4, 6, ... Four byte reads at addresses 4,5,6,7 will return the same data your read with a single DoubleWord read at address 4. Please note that this is valid only for Avalon side, if you master implements a bridge with another bus system: the addressing mode on the other side depends on your actual implementation.

[Altera_Forum]

Well, then my system behaves really strange. 

 For example my Avalon Uart is mapped to Byte Adresses 0x08000000 - 0x0800003F. When my Master is transmitting to address 0x02000000 everything works fine. So I divide the Byte Address by four und sending this address to the Avalon Bus. If my Master wants to transmit s.th. to address 0x08000000 nothing happens... and that would be the right one as you mentioned...wouldn't it?

[Altera_Forum]

When performing byte accesses you should still align the address to 4 byte boundaries for a 32-bit master. For example if you wanted to do byte writes sequentially you would use these combinations: 

 Address Byte enables 0 0001 0 0010 0 0100 0 1000 4 0001 4 0010 etc....  So above address 0, 1, 2, 3, 4, 5, etc... are written to one byte at a time. Typically I mask the LSBs of the address in my own masters based on the width of the master. So for a 32-bit master I would mask the address with & 32'hFFFFFFFC. Then I decode and shift the byte enables based on the width and alignment of my access (hard to explain in text..... see the write master in the modular SGDMA up on the alterawiki for details).

[Altera_Forum]

Yes, I understand what you mean. But I really don't understand why my UART is being written when the address, which is "leaving" my master, is 0x02000000 and the UART is mapped to 0x08000000 in Qsys.  

In Qsys you see Byte Addresses. So it shouldn't work in my oppinion or am I wrong?  Edit: I analyzed my system further more.  I have 128 MB SDRAM (0x00000000 - 0x08000000; Byte Address) and I'm using the SDRAM Controller from Qsys. Its Avalon Interface has a 25 Bit wide Address Bus, so it is addressable from 0x00000000 to 0x02000000, which mean DoubleWord Addresses. So if my Master would act like you said and transferring Byte Addresses a write to address 0x00023FF0 should be translated from the Avalon Switch Fabric into 0x00008FFC because of the address width of the SDRAM Controller, is this right? But, in fact, the address im seeing in ModelSim is the same my master transmits, 0x00023FF0. So I think my master is working correct with sending DoubleWord Addresses, isn't it? It seems like Qsys knows that my Master is issueing 32Bit addresses....  By the way: In the cpmponent editor, Interfaces Tab, I have the choice of the address units. What's the difference between "symbols" and "words"? When I change the "Bits per symbol" value from 8 to another value I'm getting an error because I have 4 Bits of byteenable. Well, that matches my 32 Bit data width. But what happens if I change the "address units"??? Is it possible that my system works because I have also a 32 Bit address width?

[Altera_Forum]

Ok, when I'm changing the address width to 30 Bits, the Avalon Switch Fabric translates the address I mentioned in my previous post (0x00023FF0) into 0x00008FFC.  

 Summary:  -With an adress width of 32 Bits Qsys handles the addresses as Double Word addresses -With an adress width of 30 Bits Qsys handles the addresses as Byte addresses  How can this be? Is this a bug in Qsys?

[Altera_Forum]

Masters use byte addressing and slaves use word addressing (typically). Qsys lets you use any combination of byte/word addressing for masters and slaves but the defaults are masters--> byte, slaves --> word for historical (SOPC Builder) reasons. 

 So your master presents a byte address to the fabric and by the time the address arrives to the slave interface it should be a word offset into the slave address space. So for example if I wanted a 32-bit master to access the four words of a 32-bit memory living at address 0x1000 I would expect this:    Master Address Slave Address 0x1000 0x0 0x1004 0x4 0x1008 0x8 0x100C 0xC    The byte enables that reach the slave interface tell the slave which bytes are being accessed within a word.

[Altera_Forum]

Yes I understand this, thanks. And my system is acting like you described in your last post. 

But: -With an adress width of 32 Bits Qsys handles the addresses as Double Word addresses -With an adress width of 30 Bits Qsys handles the addresses as Byte addresses And this without changing the behaviour of my master. So is there any switch int the .tcl-files where I can tell Qsys that my master is issueing byte adresses even with 32 Bit wide address signal? In fact thats exactly what it does NOT. :)  Its really strange but if I put an avalon master translator between my own master and all the other slaves of the system it recognizes the addresses as byte addresses. And yes, the two interfaces (master and slave) of the translator agent are set up equaly! So it seems to me that Qsys (or the fabric) does not recognize that my master is issueing byte access!!!

[Altera_Forum]

The behavior you are describing is news to me so that is not the intended functionality. I haven't checked the bug list for Qsys in a while but you might be running into a known issue. If it's not documented as a known issue I recommend opening a service request. 

 This is the .tcl command that controls whether a master/slave uses bytes(symbol) or word addressing.   set_interface_property <master or slave interface name> addressUnits <"Symbols" or "Words">

[Altera_Forum]

OK thanks, I started a service request. 

The .tcl command is in my file already, so this should not be the mistake...  Michl

[Altera_Forum]

I beg your pardon? <-- Obsolete due to erased spam reply before this post.

[Altera_Forum]

The only other workaround I can think of is maybe if you switch the master over to using word addressing this problem might go away at any width of the master address. So you just statically shift the address right before presenting it to the fabric and changing that .tcl command to use words instead of symbols. The shift will be >> (log2(datawidth/8)).