Mixed language ModelSim/Questa simulations with altera_mf

[david_]

Hi

I have a mixed language design using SystemVerilog, Verilog and VHDL. In this design there are a number of Intel FPGA components, which are either VHDL or Verilog.

I am having an issue when trying to simulate the system as a whole, which I think is due to altera_mf being used in both languages. If I compile the verilog version of altera_mf my VHDL components fail to simulate. If I compile altera_mf in Verilog the opposite is true.

The commands I am using when compiling altera_mf in VHDL are:

vlib altera_mf vmap altera_mf altera_mf vcom -work lpm -2008 -explicit "$(QUARTUS_HOME)/eda/sim_lib/altera_mf_components.vhd" vcom -work lpm -2008 -explicit "$(QUARTUS_HOME)/eda/sim_lib/altera_mf.vhd"

The command I use when compiling altera_mf in Verilog is:

vlog -work altera_mf $(QUARTUS_HOME)/eda/sim_lib/altera_mf.v

Everything seems to compile fine, the issue is after the vsim command from my Questa makefile:

vsim -L altera_mf -L lpm -64 -voptargs="+acc" -lib ${library} ${top_level} +UVM_TESTNAME=${test_case} +UVM_VERBOSITY=${uvm_verbosity} -do "do wave.tcl; run -all"

The Verilog error I am getting is from an altsyncram and complains about the lines for altsyncram_component.<parameters> being "Illegal target for defparam."

The VHDL error is from an altsqrt component with the following message: "(vopt-1130) Port "ena" of entity "altsqrt" is not in the component being instantiated."

Compiling altera_mf in verilog and VHDL appears to produce different results. Can you see anything wrong with what I am doing? Alternatively is there another way I run a simulation with both Intel Verilog and VHDL IP?

Thank you in advance

[Abe · Accepted solution]

If you're using the Intel Edition ModelSim software, you need not compile the FPGA device libraries again. All you need to do is to include them in the vsim command using the -L <lib_name> .

altera_mf for VHDL

and altera_mf_ver for Verilog

For ex,

vsim -work ... -L altera_mf_ver include any other device specific libraries this way. On the safer side you could add both VHDL as well as Verilog libraries to the simulation using the -L altera_mf -L altera_mf_ver ... options and try.

[david_]

Hi Abe,

Great thank you for the help, I have followed your advice and it is working now. I am not using Intel Edition, so used the following code:

vlog -work altera_mf_ver $(QUARTUS_HOME)/eda/sim_lib/altera_mf.v   vlib altera_mf vmap altera_mf altera_mf vcom -work altera_mf -2008 -explicit "$(QUARTUS_HOME)/eda/sim_lib/altera_mf_components.vhd" vcom -work altera_mf -2008 -explicit "$(QUARTUS_HOME)/eda/sim_lib/altera_mf.vhd"   vsim -L altera_mf_ver -64 -voptargs="+acc" -lib ${library} ${top_level} +UVM_TESTNAME=${test_case} +UVM_VERBOSITY=${uvm_verbosity} -do "do wave.tcl; run -all"

David