ModelSim-Altera Problem with PLL IP Core

Altera_Forum · ‎02-01-2015

I have some simple VHDL code. One file has an UNSIGNED counter: signal count : unsigned(3 downto 0);

The TOP level entity has the clock as input. If I use this clock for the counter which is an instantiated

entity the counter works.

If a use a clock output from a PLL the counter does not work. Not only that, but the counter is not reset to 0

when the reset pulse occurs.

The PLL clock is causing some simulation problems.

Any idea?

Thanks.

Altera_Forum · ‎02-01-2015

Found the problem.

My code uses a "synchronous" reset. If one uses a reset on the PLL then all clocks are stopped during the reset.

Thus, no reset code will be executed.!

Solution: Permanently tie PLL reset to GND.