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17268 Discussions

ModelSim : Altera_Starter_Edition VS Altera_web_edition

Altera_Forum
Honored Contributor II
2,493 Views

Hi, 

 

you can find modelsim for altera here : https://www.altera.com/support/software/download/eda_software/modelsim/msm-index.jsp 

 

 

I am actually using ModelSim 6.3g Web Edition for behavior simulation (no .vho simulated) 

 

I wonder what are the main differences between altera starter edition and altera web edition 

 

Both are limited to 100'000 lines of VHDL xor Verilog and are slower than Altera paid version. 

 

but what other differences, limitations ? 

time limited, features disabled, advertising message , no outputs, no cursors, limited wave form .......... ?
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Altera_Forum
Honored Contributor II
1,644 Views

The Altera Starter Edition is replacing the Web Edition. I believe the new Starter edition supports Verilog AND VHDL?

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Altera_Forum
Honored Contributor II
1,644 Views

AFAIK the Altera editions of Modelsim still only support a single language per project. You can have different projects in either VHDL or Verilog, but you can't mix VHDL and Verilog in a single Modelsim project. 

You need to order a license from Mentor Graphics if you want to mix languages.
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Altera_Forum
Honored Contributor II
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I just tried a project with mixed languages on Altera's modelsim starter edition and it worked. By mixed languages I mean some files are in VHDL and some were in Verilog. You cannot have true mixed language where VHDL and verilog are in the same file. 

 

The starter edition is also faster than the web edition.
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Altera_Forum
Honored Contributor II
1,644 Views

ModelSim comparison: 

http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html 

 

i just tried mixed language in ModelSim-Altera 6.5b (with 9.1sp1) and got:# ALTERA version supports only a single HDL 

 

this was with a Verilog counter instantiated in VHDL with a VHDL test bench, all separate files.
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Altera_Forum
Honored Contributor II
1,644 Views

Sorry, you're right, the sim I was compiling wasnt actually using the VHDL files...

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